Abstract: The techniques described herein relate to digitally controlled delay line gain calibration using error injection. An example apparatus includes a digitally controlled delay line (DCDL) with a DCDL output and configured to: receive a clock signal to be output from a voltage-controlled oscillator, and delay the clock signal to generate a first delayed clock signal. The apparatus further includes an error injection circuit with a first error injection input and a second error injection input, the first error injection input coupled to the DCDL output. The apparatus additionally includes a phase controller with a phase controller output coupled to the second error injection input, the phase controller configured to, in response to a pseudorandom binary sequence signal, instruct the error injection circuit to generate a second delayed clock signal based on a delay of the first delayed clock signal.

Abstract: A probe measurement system for measuring the electrical characteristics of integrated circuits or other microelectronic devices at high frequencies.

Abstract: A probe measurement system for measuring the electrical characteristics of integrated circuits or other microelectronic devices at high frequencies.

Abstract: A probe measurement system for measuring the electrical characteristics of integrated circuits or other microelectronic devices at high frequencies.

Abstract: A probe measurement system for measuring the electrical characteristics of integrated circuits or other microelectronic devices at high frequencies.

Abstract: A probe measurement system for measuring the electrical characteristics of integrated circuits or other microelectronic devices at high frequencies.

Abstract: A method and test structures are disclosed for characterizing interconnects of an integrated circuit. The method provides a set of test structures and determines a unit impedance property of each test structure, desirably using S-parameter measurements. A reference impedance data set is then formulated that characterizes the impedance of an integrated circuit manufacturing technology and that can be used to characterize the impedance of interconnects of the chip made by the technology. Each test structure desirably comprises a ground grid and a signal line, and is characterized by values of a set of predetermined attributes such as layer location of the respective ground grid, grid density, layer association, width and length of the respective signal line.