Abstract: An extreme ultraviolet (EUV) mask including an absorber structure is disclosed. The absorber structure may include at least one slanted and/or concave sidewall. The absorber structure may include a sidewall including a step. A method of forming an absorber for an EUV mask is disclosed. The method may include etching an absorber layer using a mask to form an absorber structure having a sidewall wherein an outer edge of the top surface of the sidewall is closer to a central vertical axis of the absorber structure than an outer edge of the bottom surface of the sidewall. The method may include performing additional etching steps to form a step along the sidewall of the absorber structure. The etching may include combinations of anisotropic etching in different directions, and/or isotropic etching. The method may include etching an absorber layer including multiple absorber layers having different material properties on the ML reflector.

Abstract: An extreme ultraviolet (EUV) mask including an absorber structure is disclosed. The absorber structure may include at least one slanted and/or concave sidewall. The absorber structure may include a sidewall including a step. A method of forming an absorber for an EUV mask is disclosed. The method may include etching an absorber layer using a mask to form an absorber structure having a sidewall wherein an outer edge of the top surface of the sidewall is closer to a central vertical axis of the absorber structure than an outer edge of the bottom surface of the sidewall. The method may include performing additional etching steps to form a step along the sidewall of the absorber structure. The etching may include combinations of anisotropic etching in different directions, and/or isotropic etching. The method may include etching an absorber layer including multiple absorber layers having different material properties on the ML reflector.

Abstract: A processor receives an integrated circuit design, divides the integrated circuit design into a test portion and a remaining portion, and adds sub-resolution assist features (SRAFs) having different size and spacing parameters to the test portion of the integrated circuit design to generate a single test pattern. Exposure and development equipment performs a single exposure and development process of the single test pattern to produce a single test photoresist. The processor analyzes the single test photoresist to determine which of the size and spacing parameters are unacceptable and which are acceptable, based on differences between the single test photoresist and a model photoresist that the test portion of the integrated circuit design without the SRAFs would produce. The processor adds SRAFs having the acceptable size and spacing parameters to the remaining portion of the integrated circuit design.

Abstract: A processor receives an integrated circuit design, divides the integrated circuit design into a test portion and a remaining portion, and adds sub-resolution assist features (SRAFs) having different size and spacing parameters to the test portion of the integrated circuit design to generate a single test pattern. Exposure and development equipment performs a single exposure and development process of the single test pattern to produce a single test photoresist. The processor analyzes the single test photoresist to determine which of the size and spacing parameters are unacceptable and which are acceptable, based on differences between the single test photoresist and a model photoresist that the test portion of the integrated circuit design without the SRAFs would produce. The processor adds SRAFs having the acceptable size and spacing parameters to the remaining portion of the integrated circuit design.

Abstract: Methods, program products, and systems for improving optical proximity correction (OPC) calibration, and automatically determining a minimal number of clips, are disclosed. The method can include using a computing device to perform actions including: calculating a total relevancy score for a projected sample plan including a candidate clip, and wherein the relevancy score is derived from at least one relevancy criterion and a relevancy weight; calculating a relevancy score for the candidate clip, the relevancy score for the candidate clip being a contribution from the candidate clip to the total relevancy score; and adding the candidate clip to a sample plan for the IC layout and removing the candidate clip from the plurality of clips in response a difference in relevancy score between the projected sample plan and one or more previous sample plans substantially fitting a non-linear relevancy score function.

Abstract: Methods, program products, and systems for improving optical proximity correction (OPC) calibration, and automatically determining a minimal number of clips, are disclosed. The method can include using a computing device to perform actions including: calculating a total relevancy score for a projected sample plan including a candidate clip, and wherein the relevancy score is derived from at least one relevancy criterion and a relevancy weight; calculating a relevancy score for the candidate clip, the relevancy score for the candidate clip being a contribution from the candidate clip to the total relevancy score; and adding the candidate clip to a sample plan for the IC layout and removing the candidate clip from the plurality of clips in response a difference in relevancy score between the projected sample plan and one or more previous sample plans substantially fitting a non-linear relevancy score function.

Abstract: A method for optical proximity correction (OPC) model accuracy verification for a semiconductor product includes generating a multifeature test pattern, the multifeature test pattern comprising a plurality of features selected from the semiconductor product; exposing and printing the multifeature test pattern on a test wafer under a process condition; generating an OPC model of the semiconductor product for the process condition; and comparing the test wafer to the OPC model to verify the accuracy of the OPC model.

Abstract: A method for optical proximity correction (OPC) model accuracy verification for a semiconductor product includes generating a multifeature test pattern, the multifeature test pattern comprising a plurality of features selected from the semiconductor product; exposing and printing the multifeature test pattern on a test wafer under a process condition; generating an OPC model of the semiconductor product for the process condition; and comparing the test wafer to the OPC model to verify the accuracy of the OPC model.

Abstract: A method of training an Optical Proximity Correction (OPC) model comprises symmetrizing a complex design to be a test pattern having orthogonal symmetry. Symmetrizing may comprise establishing a axis of symmetry passing through the design, thereby dividing the design into two portions; deleting one of the two portions; and mirror-imaging the other of the two portions about the axis of symmetry. The design may be centered.

Abstract: A method of calibrating a lithographic process model is provided. The method includes providing a test pattern that includes a plurality of shapes; transferring the test pattern onto a photo-mask forming a resist image of the test pattern using the photo-mask; collecting model calibration data from the resist image; and calibrating the lithographic process model using the model calibration data, wherein the plurality of shapes of the test pattern have at least a first shape and a second shape, and distances from an edge of the first shape to an edge of the second shape over a range thereof, when being measured parallel to each other, differ from each other.

Abstract: A method of calibrating a model of a lithographic process includes a plurality of test features each having different widths that vary from a resolvable feature width that is known to be resolvable by the lithographic process, to a width that is known not to be resolvable by the lithographic process. The test features and patterns are specifically designed to include features that approach or exceed the resolution of the lithographic process, and range from known resolvable patterns to patterns that are expected to fail to be resolved. The printed test patterns are inspected for printability and the extremum intensity values associated with neighboring printable and non-printable test patterns are used to determine a constant threshold value to be used in a resist process model.

Abstract: A method of calibrating a model of a lithographic process includes a plurality of test features each having different widths that vary from a resolvable feature width that is known to be resolvable by the lithographic process, to a width that is known not to be resolvable by the lithographic process. The test features and patterns are specifically designed to include features that approach or exceed the resolution of the lithographic process, and range from known resolvable patterns to patterns that are expected to fail to be resolved. The printed test patterns are inspected for printability and the extremum intensity values associated with neighboring printable and non-printable test patterns are used to determine a constant threshold value to be used in a resist process model.

Abstract: A process for fabricating a semiconductor device, including applying an immersion lithography medium to a surface of a semiconductor wafer; exposing a material on the surface of the semiconductor wafer to electromagnetic radiation having a selected wavelength; and applying supercritical carbon dioxide to the semiconductor wafer to remove the immersion lithography medium from the surface of the semiconductor wafer. In one embodiment, the process includes recovery of the immersion lithography medium.

Abstract: A method of training an Optical Proximity Correction (OPC) model comprises symmetrizing a complex design to be a test pattern having orthogonal symmetry. Symmetrizing may comprise establishing a axis of symmetry passing through the design, thereby dividing the design into two portions; deleting one of the two portions; and mirror-imaging the other of the two portions about the axis of symmetry. The design may be centered.

Abstract: A method of operating an immersion lithography system, including steps of immersing at least a portion of a wafer to be exposed in an immersion medium, wherein the immersion medium comprises at least one bubble; directing an ultrasonic wave through at least a portion of the immersion medium to disrupt and/or dissipate the at least one bubble; and exposing the wafer with an exposure pattern by passing electromagnetic radiation through the immersion medium subsequent to the directing. Also disclosed is a monitoring and control system for an immersion lithography system.