Patents by Inventor Amrinder S. Barn
Amrinder S. Barn has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11688486Abstract: An apparatus includes a memory circuit that includes a plurality of sub-arrays. The memory circuit is configured to implement a retention mode according to test information indicating voltage sensitivities for the plurality of sub-arrays. The apparatus also includes a voltage control circuit coupled to a power supply node. The voltage control circuit is configured, in response to activation of the retention mode for the plurality of sub-arrays, to generate, based on the test information, at least two different retention voltage levels for different ones of the plurality of sub-arrays. The at least two different retention voltage levels are lower than a power supply voltage level of the power supply node.Type: GrantFiled: August 16, 2021Date of Patent: June 27, 2023Assignee: Apple Inc.Inventors: Shahzad Nazar, Mohamed H. Abu-Rahma, Amrinder S. Barn
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Publication number: 20220028479Abstract: An apparatus includes a memory circuit that includes a plurality of sub-arrays. The memory circuit is configured to implement a retention mode according to test information indicating voltage sensitivities for the plurality of sub-arrays. The apparatus also includes a voltage control circuit coupled to a power supply node. The voltage control circuit is configured, in response to activation of the retention mode for the plurality of sub-arrays, to generate, based on the test information, at least two different retention voltage levels for different ones of the plurality of sub-arrays. The at least two different retention voltage levels are lower than a power supply voltage level of the power supply node.Type: ApplicationFiled: August 16, 2021Publication date: January 27, 2022Inventors: Shahzad Nazar, Mohamed H. Abu-Rahma, Amrinder S. Barn
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Patent number: 11094395Abstract: An apparatus includes a memory circuit that includes a plurality of sub-arrays. The memory circuit is configured to implement a retention mode according to test information indicating voltage sensitivities for the plurality of sub-arrays. The apparatus also includes a voltage control circuit coupled to a power supply node. The voltage control circuit is configured, in response to activation of the retention mode for the plurality of sub-arrays, to generate, based on the test information, at least two different retention voltage levels for different ones of the plurality of sub-arrays. The at least two different retention voltage levels are lower than a power supply voltage level of the power supply node.Type: GrantFiled: November 7, 2019Date of Patent: August 17, 2021Assignee: Apple Inc.Inventors: Shahzad Nazar, Mohamed H. Abu-Rahma, Amrinder S. Barn
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Publication number: 20210142863Abstract: An apparatus includes a memory circuit that includes a plurality of sub-arrays. The memory circuit is configured to implement a retention mode according to test information indicating voltage sensitivities for the plurality of sub-arrays. The apparatus also includes a voltage control circuit coupled to a power supply node. The voltage control circuit is configured, in response to activation of the retention mode for the plurality of sub-arrays, to generate, based on the test information, at least two different retention voltage levels for different ones of the plurality of sub-arrays. The at least two different retention voltage levels are lower than a power supply voltage level of the power supply node.Type: ApplicationFiled: November 7, 2019Publication date: May 13, 2021Inventors: Shahzad Nazar, Mohamed H. Abu-Rahma, Amrinder S. Barn
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Patent number: 10523194Abstract: A power switch control circuit is disclosed. A sensor circuit may determine a leakage current of a power switch coupled to a power supply signal and a power terminal of a circuit block. The power switch may be configured to selectively couple or decouple the circuit block from the power supply signal using a switch control signal. The switch control circuit may, in response to receiving a request to open the power switch, determine a target voltage level that is greater than a voltage level of the power supply signal for the switch control signal using the leakage current, and transition the switch control signal from an initial voltage to the target voltage level.Type: GrantFiled: September 27, 2017Date of Patent: December 31, 2019Assignee: Apple Inc.Inventors: Jaroslav Raszka, Amrinder S. Barn, Victor Zyuban, Shingo Suzuki, Ajay Kumar Bhatia, Mohamed H. Abu-Rahma, Shahzad Nazar, Greg M. Hess
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Patent number: 10340900Abstract: In an embodiment, an apparatus includes a first latch including a true storage node and a complement storage node, a discharge circuit, and a second latch. The first latch may pre-charge the true storage node and the complement storage node to a first voltage level using a clock signal. The discharge circuit may, in response to a determination that a scan mode signal is asserted, selectively discharge either the true storage node or the complement storage node based on a value of a scan data signal, and otherwise may selectively discharge either the true storage node or the complement storage node based on a value of a data signal. The second latch may store a value of a data bit based on a voltage level of the true storage node and a voltage level of the complement storage node.Type: GrantFiled: December 22, 2016Date of Patent: July 2, 2019Assignee: Apple Inc.Inventors: Amrinder S. Barn, Bo Zhao, Michael A. Dreesen
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Publication number: 20190097622Abstract: A power switch control circuit is disclosed. A sensor circuit may determine a leakage current of a power switch coupled to a power supply signal and a power terminal of a circuit block. The power switch may be configured to selectively couple or decouple the circuit block from the power supply signal using a switch control signal. The switch control circuit may, in response to receiving a request to open the power switch, determine a target voltage level that is greater than a voltage level of the power supply signal for the switch control signal using the leakage current, and transition the switch control signal from an initial voltage to the target voltage level.Type: ApplicationFiled: September 27, 2017Publication date: March 28, 2019Inventors: Jaroslav Raszka, Amrinder S. Barn, Victor Zyuban, Shingo Suzuki, Ajay Kumar Bhatia, Mohamed H. Abu-Rahma, Shahzad Nazar, Greg M. Hess
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Publication number: 20180181193Abstract: In an embodiment, an apparatus includes a first latch including a true storage node and a complement storage node, a discharge circuit, and a second latch. The first latch may pre-charge the true storage node and the complement storage node to a first voltage level using a clock signal. The discharge circuit may, in response to a determination that a scan mode signal is asserted, selectively discharge either the true storage node or the complement storage node based on a value of a scan data signal, and otherwise may selectively discharge either the true storage node or the complement storage node based on a value of a data signal. The second latch may store a value of a data bit based on a voltage level of the true storage node and a voltage level of the complement storage node.Type: ApplicationFiled: December 22, 2016Publication date: June 28, 2018Inventors: Amrinder S. Barn, Bo Zhao, Michael A. Dreesen
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Patent number: 9324386Abstract: A device for comparing voltage levels of a pair of input signals is presented. The device may include a pre-amp circuit and a differential amplifier. The pre-amp circuit may be configured to receive a first input signal and a second input signal, adjust a voltage level of each of the pair of input signals, and assert a control signal after a pre-determined period of time from the assertion of an enable signal. The differential amplifier may be configured to amplify a voltage difference between the first input signal and the second input signal dependent upon the adjusted voltage level of the pair of input signals in response to the assertion of the control signal.Type: GrantFiled: January 17, 2014Date of Patent: April 26, 2016Assignee: Apple Inc.Inventors: Ajay Kumar Bhatia, Amrinder S Barn
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Patent number: 9311967Abstract: A system, a memory device and a method are contemplated in which the apparatus may include a plurality of memory cells, a plurality of voltage reduction circuits, and control circuitry. The plurality of voltage reduction circuits may be configured to reduce a voltage level of a power supply coupled to the plurality of memory cells. The control circuitry may be configured to select one of the voltage reduction circuits based on one or more operating parameters. The control circuitry may be further configured to activate the selected voltage reduction circuit upon receiving a write command directed towards the memory cells. The control circuitry may be further configured to execute the write command. Upon completion of the write command, the control circuitry may be further configured to de-activate the selected one of the voltage reduction circuits.Type: GrantFiled: May 30, 2014Date of Patent: April 12, 2016Assignee: Apple Inc.Inventors: Ajay Kumar Bhatia, Anshul Y. Mehta, Amrinder S. Barn, Greg M. Hess
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Publication number: 20150348600Abstract: A system, a memory device and a method are contemplated in which the apparatus may include a plurality of memory cells, a plurality of voltage reduction circuits, and control circuitry. The plurality of voltage reduction circuits may be configured to reduce a voltage level of a power supply coupled to the plurality of memory cells. The control circuitry may be configured to select one of the voltage reduction circuits based on one or more operating parameters. The control circuitry may be further configured to activate the selected voltage reduction circuit upon receiving a write command directed towards the memory cells. The control circuitry may be further configured to execute the write command. Upon completion of the write command, the control circuitry may be further configured to de-activate the selected one of the voltage reduction circuits.Type: ApplicationFiled: May 30, 2014Publication date: December 3, 2015Applicant: Apple Inc.Inventors: Ajay Kumar Bhatia, Anshul Y. Mehta, Amrinder S. Barn, Greg M. Hess
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Publication number: 20150207462Abstract: A device for comparing voltage levels of a pair of input signals is presented. The device may include a pre-amp circuit and a differential amplifier. The pre-amp circuit may be configured to receive a first input signal and a second input signal, adjust a voltage level of each of the pair of input signals, and assert a control signal after a pre-determined period of time from the assertion of an enable signal. The differential amplifier may be configured to amplify a voltage difference between the first input signal and the second input signal dependent upon the adjusted voltage level of the pair of input signals in response to the assertion of the control signal.Type: ApplicationFiled: January 17, 2014Publication date: July 23, 2015Applicant: Apple Inc.Inventors: Ajay Kumar Bhatia, Amrinder S. Barn