Patents by Inventor Amrita Singh
Amrita Singh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 12692034Abstract: Various aspects disclosed relate to a sterilization packaging. The sterilization packaging includes a first major surface that is substantially opaque. The sterilization packaging further includes a second major surface. The sterilization packaging further includes an opaque portion and a substantially transparent portion.Type: GrantFiled: October 7, 2025Date of Patent: July 28, 2026Assignee: STERIS CorporationInventors: Samantha Statham, Amrita Singh, Renee Buthe, Aaron Mertens, Lisa Chen
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Patent number: 12677599Abstract: A semiconductor device is fabricated by: forming a shadow wall on a substrate; subsequently growing a nanowire of semiconductor material on the substrate; and directionally depositing a layer of a further material on the nanowire from a direction selected such that the shadow wall casts a shadow on the nanowire, the shadow being a region in which the further material is not deposited. The nanowire is vertically orientated relative to the substrate. The shadow wall comprises a base portion and a bridge portion. The bridge portion overhangs the substrate and is supported by the base portion. Patterning of the further material may be achieved without the use of etching, thereby avoiding damage to the semiconductor. Also provided is a semiconductor-superconductor hybrid device; a quantum computing device comprising the semiconductor-superconductor hybrid device; and a shadow wall for controlling directional deposition of a material.Type: GrantFiled: July 16, 2020Date of Patent: July 7, 2026Assignee: Microsoft Technology Licensing, LLCInventors: Amrita Singh, Elvedin Memisevic, Peter Krogstrup Jeppesen
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Patent number: 12646657Abstract: The present invention relates to an unsymmetrical squaraine dye of formula (I) and process for the preparation thereof. The process includes dissolving a 3-cycloalkene-1,2-dione compound in acetone and aqueous HCl to afford a semisquaraine compound. The process includes refluxing the semisquaraine compound and phenyl carboxylic acid dissolved in solvent to afford the unsymmetrical squaraine dye. Further, the present invention relates to an electronic device with an enhanced device efficiency containing a dye of formula (I) co-sensitized with a squaraine dye.Type: GrantFiled: March 17, 2022Date of Patent: June 2, 2026Assignee: Council of Scientific and Industrial ResearchInventors: Jayaraj Nithyanandhan, Ambarish Kumar Singh, Amrita Singh
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Patent number: 12635428Abstract: A shadow wall for controlling directional deposition of a material is arranged on a substrate. The shadow wall comprises a base portion and a bridge portion. The base portion is arranged on the substrate and is configured to support the bridge portion. The bridge portion overhangs the substrate. The shadow wall may have improved compatibility with non-directional deposition processes, because adatoms on the surface of the substrate may diffuse under the bridge. Also provided are a method of fabricating a device using the shadow wall, and a method of fabricating the shadow wall.Type: GrantFiled: February 28, 2020Date of Patent: May 19, 2026Assignee: Microsoft Technology Licensing, LLCInventors: Elvedin Memisevic, Amrita Singh, Pavel Aseev
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Patent number: 12581869Abstract: One aspect provides semiconductor-superconductor hybrid device comprises a substrate, a first semiconductor component arranged on the substrate, a superconductor component arranged to be capable of energy level hybridisation with the first semiconductor component, and a second semiconductor component arranged as a gate electrode for gating the first semiconductor component. Another aspect provides a semiconductor-superconductor hybrid device, comprising: a substrate; a semiconductor component arranged on the substrate; a gate electrode for gating the semiconductor component; and a superconductor component capable of undergoing energy level hybridisation with the semiconductor component; wherein the gate electrode is arranged in a channel in the substrate. Also provided are methods of fabricating the semiconductor-superconductor hybrid devices.Type: GrantFiled: March 31, 2020Date of Patent: March 17, 2026Assignee: Microsoft Technology Licensing, LLCInventors: Marina Quintero Pérez, David Johannes Van Woerkom, Vinay Kumar Chinni, Amrita Singh
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Publication number: 20260035116Abstract: Various aspects disclosed relate to a sterilization packaging. The sterilization packaging includes a first major surface that is substantially opaque. The sterilization packaging further includes a second major surface. The sterilization packaging further includes an opaque portion and a substantially transparent portion.Type: ApplicationFiled: October 7, 2025Publication date: February 5, 2026Inventors: Samantha Statham, Amrita Singh, Renee Buthe, Aaron Mertens, Lisa Chen
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Patent number: 12466597Abstract: Various aspects disclosed relate to a sterilization packaging. The sterilization packaging includes a first major surface that is substantially opaque. The sterilization packaging further includes a second major surface. The sterilization packaging further includes an opaque portion and a substantially transparent portion.Type: GrantFiled: July 17, 2024Date of Patent: November 11, 2025Assignee: STERIS CorporationInventors: Samantha Statham, Amrita Singh, Renee Buthe, Aaron Mertens, Lisa Chen
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Patent number: 12412743Abstract: A method of fabricating a hollow wall for controlling directional deposition of material comprises: forming a layer of resist on a substrate; removing a portion of the resist selectively to form a channel in the resist; forming a layer of an amorphous dielectric material in the channel; and removing the resist to form the hollow wall. The channel has a front surface configured to prevent bending of a corresponding front face of the hollow wall. The hollow wall is useful for controlling deposition of material when fabricating semiconductor-superconductor hybrid devices, for example. By configuring the channel appropriately, bending of the hollow wall can be prevented, allowing for more precise deposition of material. Also provided is a further method of fabricating a hollow wall; and a method of fabricating a device using the hollow walls.Type: GrantFiled: December 5, 2019Date of Patent: September 9, 2025Assignees: Microsoft Technology Licensing, LLC, Delft University of TechnologyInventors: Pavel Aseev, Ekaterina Chernysheva, Amrita Singh, Guanzhong Wang
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Publication number: 20250280014Abstract: A log of resource modifications in a cloud computing environment is incrementally transmitted to a threat management facility. The threat management facility can analyze the log, along with related identity information, to determine when additional information might be useful to detect a malicious misconfiguration of cloud resources. The threat management facility can then access additional information through an application programming interface, and the additional information can be used to perform a detection, initiate remediation, and so forth. This approach advantageously permits fast detection of potential threats based on the continuous log reporting, while deferring high-latency API access to the cloud platform (and/or other computationally expensive operations) until appropriate for confirming detections that are raised based on the log.Type: ApplicationFiled: March 2, 2025Publication date: September 4, 2025Inventors: Arun Singh, Amrita Singh, Sachin Kumar
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Publication number: 20250026522Abstract: Various aspects disclosed relate to a sterilization packaging. The sterilization packaging includes a first major surface that is substantially opaque. The sterilization packaging further includes a second major surface. The sterilization packaging further includes an opaque portion and a substantially transparent portion.Type: ApplicationFiled: July 17, 2024Publication date: January 23, 2025Inventors: Samantha Statham, Amrita Singh, Renee Buthe, Aaron Mertens, Lisa Chen
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Patent number: 12178141Abstract: There is provided a method of selectively patterning a device structure. A hollow shadow wall is formed on a substrate. The hollow shadow wall is formed of a base lying on a surface of the substrate, and one or more side walls connected to the base. The one or more side walls extend away from the surface of the substrate and around the base to define an internal cavity of the hollow shadow wall. A device structure supported by the substrate adjacent to the shadow wall is selectively patterned by using a deposition beam to selectively deposit a layer of deposition material on the device structure. The deposition beam has a non-zero angle of incidence relative to a normal to the surface of the substrate and an orientation in the plane of the substrate's surface, such that the shadow wall prevents deposition on a surface portion of the device structure within a shadow region defined by the shadow wall.Type: GrantFiled: May 27, 2021Date of Patent: December 24, 2024Assignee: Microsoft Technology Licensing, LLCInventors: Senja Ramakers, Pavel Aseev, Amrita Singh, Jie Shen, Leonardus P. Kouwenhoven
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Publication number: 20230276718Abstract: A semiconductor device is fabricated by: forming a shadow wall on a substrate; subsequently growing a nanowire of semiconductor material on the substrate; and directionally depositing a layer of a further material on the nanowire from a direction selected such that the shadow wall casts a shadow on the nanowire, the shadow being a region in which the further material is not deposited. The nanowire is vertically orientated relative to the substrate. The shadow wall comprises a base portion and a bridge portion. The bridge portion overhangs the substrate and is supported by the base portion. Patterning of the further material may be achieved without the use of etching, thereby avoiding damage to the semiconductor. Also provided is a semiconductor-superconductor hybrid device; a quantum computing device comprising the semiconductor-superconductor hybrid device; and a shadow wall for controlling directional deposition of a material.Type: ApplicationFiled: July 16, 2020Publication date: August 31, 2023Applicant: Microsoft Technology Licensing, LLCInventors: Amrita Singh, Elvedin Memisevic, Peter Krogstrup Jeppesen
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Publication number: 20230147168Abstract: One aspect provides semiconductor-superconductor hybrid device comprises a substrate, a first semiconductor component arranged on the substrate, a superconductor component arranged to be capable of energy level hybridisation with the first semiconductor component, and a second semiconductor component arranged as a gate electrode for gating the first semiconductor component. Another aspect provides a semiconductor-superconductor hybrid device, comprising: a substrate; a semiconductor component arranged on the substrate; a gate electrode for gating the semiconductor component; and a superconductor component capable of undergoing energy level hybridisation with the semiconductor component; wherein the gate electrode is arranged in a channel in the substrate. Also provided are methods of fabricating the semiconductor-superconductor hybrid devices.Type: ApplicationFiled: March 31, 2020Publication date: May 11, 2023Applicant: Microsoft Technology Licensing, LLCInventors: Marina QUINTERO PÉREZ, David Johannes VAN WOERKOM, Vinay Kumar CHINNI, Amrita SINGH
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Publication number: 20230106283Abstract: A shadow wall for controlling directional deposition of a material is arranged on a substrate. The shadow wall comprises a base portion and a bridge portion. The base portion is arranged on the substrate and is configured to support the bridge portion. The bridge portion overhangs the substrate. The shadow wall may have improved compatibility with non-directional deposition processes, because adatoms on the surface of the substrate may diffuse under the bridge. Also provided are a method of fabricating a device using the shadow wall, and a method of fabricating the shadow wall.Type: ApplicationFiled: February 28, 2020Publication date: April 6, 2023Applicant: Microsoft Technology Licensing, LLCInventors: Elvedin MEMISEVIC, Amrita SINGH, Pavel ASEEV
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Publication number: 20230008296Abstract: A method of fabricating a hollow wall for controlling directional deposition of material comprises: forming a layer of resist on a substrate; removing a portion of the resist selectively to form a channel in the resist; forming a layer of an amorphous dielectric material in the channel; and removing the resist to form the hollow wall. The channel has a front surface configured to prevent bending of a corresponding front face of the hollow wall. The hollow wall is useful for controlling deposition of material when fabricating semiconductor-superconductor hybrid devices, for example. By configuring the channel appropriately, bending of the hollow wall can be prevented, allowing for more precise deposition of material. Also provided is a further method of fabricating a hollow wall; and a method of fabricating a device using the hollow walls.Type: ApplicationFiled: December 5, 2019Publication date: January 12, 2023Applicant: Microsoft Technology Licensing, LLCInventors: Pavel ASEEV, Ekaterina CHERNYSHEVA, Amrita SINGH, Guanzhong WANG
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Publication number: 20220288131Abstract: The present invention generally relates to novel mesoderm-derived vascular progenitor cells (meso-VPCs) and methods of producing the meso-VPCs. The present invention also relates to methods of treating a vascular disease, such as critical limb ischemia, by administering the meso-VPCs into a subject.Type: ApplicationFiled: August 27, 2020Publication date: September 15, 2022Inventors: Maria Mirotsou, Nutan Prasain, Amrita Singh, Robert Lanza
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Publication number: 20220280572Abstract: The present invention provides methods for treating vascular diseases with hemogenic endothelial cells (HEs) obtained in vitro from pluripotent stem cells. The present invention also provides compositions and methods of producing the HEs.Type: ApplicationFiled: August 27, 2020Publication date: September 8, 2022Inventors: Nagisa Sakurai, Maria Mirotsou, Nutan Prasain, Amrita Singh, Robert Lanza
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Publication number: 20220227999Abstract: The present invention relates to an unsymmetrical squaraine dye of formula (I) and process for the preparation thereof. Further, the present invention relates to an electronic device with an enhanced device efficiency containing a dye of formula (I) co-sensitized with a sqaurine dye.Type: ApplicationFiled: March 17, 2022Publication date: July 21, 2022Inventors: Jayaraj Nithyanandhan, Ambarish Kumar Singh, Amrita Singh
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Publication number: 20210296560Abstract: There is provided a method of selectively patterning a device structure. A hollow shadow wall is formed on a substrate. The hollow shadow wall is formed of a base lying on a surface of the substrate, and one or more side walls connected to the base. The one or more side walls extend away from the surface of the substrate and around the base to define an internal cavity of the hollow shadow wall. A device structure supported by the substrate adjacent to the shadow wall is selectively patterned by using a deposition beam to selectively deposit a layer of deposition material on the device structure. The deposition beam has a non-zero angle of incidence relative to a normal to the surface of the substrate and an orientation in the plane of the substrate's surface, such that the shadow wall prevents deposition on a surface portion of the device structure within a shadow region defined by the shadow wall.Type: ApplicationFiled: May 27, 2021Publication date: September 23, 2021Applicant: Microsoft Technology Licensing, LLCInventors: Senja Ramakers, Pavel Aseev, Amrita Singh, Jie Shen, Leonardus P. Kouwenhoven
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Patent number: 11024792Abstract: There is provided a method of selectively patterning a device structure. A hollow shadow wall is formed on a substrate. The hollow shadow wall is formed of a base lying on a surface of the substrate, and one or more side walls connected to the base. The one or more side walls extend away from the surface of the substrate and around the base to define an internal cavity of the hollow shadow wall. A device structure supported by the substrate adjacent to the shadow wall is selectively patterned by using a deposition beam to selectively deposit a layer of deposition material on the device structure. The deposition beam has a non-zero angle of incidence relative to a normal to the surface of the substrate and an orientation in the plane of the substrate's surface, such that the shadow wall prevents deposition on a surface portion of the device structure within a shadow region defined by the shadow wall.Type: GrantFiled: January 25, 2019Date of Patent: June 1, 2021Assignee: Microsoft Technology Licensing, LLCInventors: Senja Ramakers, Pavel Aseev, Amrita Singh, Jie Shen, Leonardus P. Kouwenhoven