Patents by Inventor Amritanshu Anand

Amritanshu Anand has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12118376
    Abstract: Disclosed herein is hardware for easing the process of changing the execution mode of a virtual machine and its associated resources. By adopting the hardware, it is possible to trigger a change in the execution mode in an automatic way, without software intervention, and without interfering with the execution of other virtual machines. In addition, in case an error has occurred for a virtual machine and it is detected, the hardware can be used to disable the resources associated with that virtual machine and generate notification of the completion this operation to other hardware, which will complete the reset of the virtual machine. By adopting the hardware, the execution mode change is simplified and offers configurability and flexibility for a system running multiple virtual machines.
    Type: Grant
    Filed: April 20, 2021
    Date of Patent: October 15, 2024
    Assignees: STMicroelectronics International N.V., STMicroeletronics Application GmbH
    Inventors: Deepak Baranwal, Amritanshu Anand, Roberto Colombo, Boris Vittorelli
  • Publication number: 20240241811
    Abstract: In general, trace and debug logic should not be affected by all functional or destructive resets of a processing system. However, certain events, such as power supply related events may be utilized to reset the trace and debug logic since the trace and debug logic may cease correct operation if the provided power supply is insufficient. In addition, it may be beneficial for a debugger to initiate requests to reset trace and debug logic. Further, fault triggers from critical path monitors may be candidates as a source of reset for the trace and debug circuitry. For example, when critical path monitors trigger a fault, the fault may be from the logic associated with either trace and debug logic or the logic which is being debugged or traced. As such, in some instances both trace and debug circuitry and the processing system may be inoperable and may need to be reset.
    Type: Application
    Filed: January 17, 2023
    Publication date: July 18, 2024
    Inventors: Avneep Kumar GOYAL, Amritanshu ANAND, Satinder Singh MALHI
  • Patent number: 11835991
    Abstract: In an embodiment, a method for managing self-tests in an integrated circuit (IC) includes: receiving built-in-self-test (BIST) configuration data; configuring a first clock to a first frequency based on the BIST configuration data; performing a first BIST test at the first frequency; configuring a second clock to a second frequency that is different from the first frequency; and performing a second BIST test at the second frequency.
    Type: Grant
    Filed: March 22, 2021
    Date of Patent: December 5, 2023
    Assignee: STMicroelectronics International N.V.
    Inventors: Amulya Pandey, Balwinder Singh Soni, Amritanshu Anand, Venkata Narayanan Srinivasan
  • Publication number: 20220334862
    Abstract: Disclosed herein is hardware for easing the process of changing the execution mode of a virtual machine and its associated resources. By adopting the hardware, it is possible to trigger a change in the execution mode in an automatic way, without software intervention, and without interfering with the execution of other virtual machines. In addition, in case an error has occurred for a virtual machine and it is detected, the hardware can be used to disable the resources associated with that virtual machine and generate notification of the completion this operation to other hardware, which will complete the reset of the virtual machine. By adopting the hardware, the execution mode change is simplified and offers configurability and flexibility for a system running multiple virtual machines.
    Type: Application
    Filed: April 20, 2021
    Publication date: October 20, 2022
    Applicants: STMicroelectronics International N.V., STMicroelectronics Application GmbH
    Inventors: Deepak BARANWAL, Amritanshu ANAND, Roberto COLOMBO, Boris VITTORELLI
  • Publication number: 20220300389
    Abstract: In an embodiment, a method for managing self-tests in an integrated circuit (IC) includes: receiving built-in-self-test (BIST) configuration data; configuring a first clock to a first frequency based on the BIST configuration data; performing a first BIST test at the first frequency; configuring a second clock to a second frequency that is different from the first frequency; and performing a second BIST test at the second frequency.
    Type: Application
    Filed: March 22, 2021
    Publication date: September 22, 2022
    Inventors: Amulya Pandey, Balwinder Singh Soni, Amritanshu Anand, Venkata Narayanan Srinivasan