Patents by Inventor Amritesh Rai

Amritesh Rai has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230397423
    Abstract: A method of forming a microelectronic device includes forming conductive interconnect structures vertically extending through isolation material to conductive contact structures coupled to pillar structures, forming a metal silicide material on the interconnect structures and the first isolation material, forming a conductive material on the metal silicide material, and forming a dielectric material over the conductive material. The method further includes forming openings vertically extending through the dielectric material, the conductive material, the metal silicide material, and the isolation material and forming additional isolation material to extend over remaining portions of the dielectric material and at least partially fill the openings. Related devices and systems are disclosed.
    Type: Application
    Filed: April 26, 2023
    Publication date: December 7, 2023
    Inventors: Pengyuan Zheng, Yongjun J. Hu, Pavan Reddy Kumar Aella, David Ross Economy, Brittany L. Kohoutek, Amritesh Rai
  • Publication number: 20230389314
    Abstract: A method used in forming a memory array comprises forming a stack comprising vertically-alternating insulative tiers and conductive tiers. Channel-material strings of memory-cell strings extend through the insulative and conductive tiers. Conductive vias are formed above and individually directly electrically coupled to individual of the channel-material strings. Digitlines are formed above and are individually directly electrically coupled to a plurality of individual of the conductive vias there-below. The forming of the digitlines comprises forming lower elemental-form tungsten directly against tops of the individual conductive vias. The lower elemental-form tungsten is exposed to oxygen-containing gas or plasma to form WOx, where “x” is greater than 0 and no more than 3.0. The WOx has a maximum thickness greater than 0 and no more than 30 Angstroms in a finished construction. Upper elemental-form tungsten is physical vapor deposited directly against the WOx.
    Type: Application
    Filed: August 2, 2022
    Publication date: November 30, 2023
    Applicant: Micron Technology, Inc.
    Inventors: Adam Barton, David H. Wells, Pengyuan Zheng, Amritesh Rai
  • Publication number: 20220415917
    Abstract: A microelectronic device comprises a stack structure comprising alternating conductive structures and insulative structures arranged in tiers, each of the tiers individually comprising a conductive structure and an insulative structure, strings of memory cells vertically extending through the stack structure, the strings of memory cells comprising a channel material vertically extending through the stack structure, and another stack structure vertically overlying the stack structure and comprising other tiers of alternating levels of other conductive structures and other insulative structures, the other conductive structures exhibiting a conductivity greater than a conductivity of the conductive structures of the stack structure. Related memory devices, electronic systems, and methods are also described.
    Type: Application
    Filed: August 26, 2022
    Publication date: December 29, 2022
    Inventors: Daniel Billingsley, Matthew J. King, Jordan D. Greenlee, Yongjun J. Hu, Tom George, Amritesh Rai, Sidhartha Gupta, Kyle A. Ritter
  • Patent number: 11527546
    Abstract: A microelectronic device comprises a stack structure comprising alternating conductive structures and insulative structures arranged in tiers, each of the tiers individually comprising a conductive structure and an insulative structure, strings of memory cells vertically extending through the stack structure, the strings of memory cells comprising a channel material vertically extending through the stack structure, and another stack structure vertically overlying the stack structure and comprising other tiers of alternating levels of other conductive structures and other insulative structures, the other conductive structures exhibiting a conductivity greater than a conductivity of the conductive structures of the stack structure. Related memory devices, electronic systems, and methods are also described.
    Type: Grant
    Filed: July 30, 2020
    Date of Patent: December 13, 2022
    Assignee: Micron Technology, Inc.
    Inventors: Daniel Billingsley, Matthew J. King, Jordan D. Greenlee, Yongjun J. Hu, Tom George, Amritesh Rai, Sidhartha Gupta, Kyle A. Ritter
  • Publication number: 20220037350
    Abstract: A microelectronic device comprises a stack structure comprising alternating conductive structures and insulative structures arranged in tiers, each of the tiers individually comprising a conductive structure and an insulative structure, strings of memory cells vertically extending through the stack structure, the strings of memory cells comprising a channel material vertically extending through the stack structure, and another stack structure vertically overlying the stack structure and comprising other tiers of alternating levels of other conductive structures and other insulative structures, the other conductive structures exhibiting a conductivity greater than a conductivity of the conductive structures of the stack structure. Related memory devices, electronic systems, and methods are also described.
    Type: Application
    Filed: July 30, 2020
    Publication date: February 3, 2022
    Inventors: Daniel Billingsley, Matthew J. King, Jordan D. Greenlee, Yongjun J. Hu, Tom George, Amritesh Rai, Sidhartha Gupta, Kyle A. Ritter