Patents by Inventor Amrith Sukumaran

Amrith Sukumaran has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11949763
    Abstract: According to an aspect, a method of data compression in a radar system comprising, converting a plurality of ranges in a first data form into a polar form, determining a plurality of logarithmic values of the plurality of ranges in the polar form, quantising the plurality of logarithmic values of the plurality of ranges with a first bit width that is fewer than a second bit width in the first data form. According to another aspect, the method further comprising quantizing the logarithmic magnitude part with a third bit width and quantising the logarithmic phase part with a fourth bit width.
    Type: Grant
    Filed: January 27, 2021
    Date of Patent: April 2, 2024
    Inventors: Amrith Sukumaran, G Ranjithkumar, Gireesh Rajendran
  • Publication number: 20220159097
    Abstract: According to an aspect, a method of data compression in a radar system comprising, converting a plurality of ranges in a first data form into a polar form, determining a plurality of logarithmic values of the plurality of ranges in the polar form, quantising the plurality of logarithmic values of the plurality of ranges with a first bit width that is fewer than a second bit width in the first data form. According to another aspect, the method further comprising quantizing the logarithmic magnitude part with a third bit width and quantising the logarithmic phase part with a fourth bit width.
    Type: Application
    Filed: January 27, 2021
    Publication date: May 19, 2022
    Applicant: Steradian Semiconductors Private Limited
    Inventors: Amrith Sukumaran, G Ranjithkumar, Gireesh Gunaranjan Rajendran
  • Patent number: 10784878
    Abstract: According to an aspect, a tri-level digital to analog converter (DAC) comprises a first set of switches turned on to cause a first analog value with a first error as an output for a first digital value, a second set of switches turned on to cause a second analog value with a second error as the output for a second digital value, wherein, both the first set of switches and the second set of switches are turned on to cause a third analog value, proportional to the first error and the second error, as the output for a digital value equal to zero, and both the first set of switches and the second set of switches are turned off to cause a fourth analog value equal to zero as the output for a fourth digital value representing a reset state.
    Type: Grant
    Filed: December 21, 2019
    Date of Patent: September 22, 2020
    Inventors: Amrith Sukumaran, Gireesh Rajendran, Ashish Lachhwani