Patents by Inventor Amritpal Singh Mundra

Amritpal Singh Mundra has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20200127984
    Abstract: An electronic circuit (200) includes one or more programmable control-plane engines (410, 460) operable to process packet header information and form at least one command, one or more programmable data-plane engines (310, 320, 370) selectively operable for at least one of a plurality of cryptographic processes selectable in response to the at least one command, and a programmable host processor (100) coupled to such a data-plane engine (310) and such a control-plane engine (410). Other processors, circuits, devices and systems and processes for their operation and manufacture are disclosed.
    Type: Application
    Filed: December 19, 2019
    Publication date: April 23, 2020
    Inventors: Amritpal Singh Mundra, Denis Roland Beaudoin
  • Patent number: 10567358
    Abstract: An electronic circuit (200) includes one or more programmable control-plane engines (410, 460) operable to process packet header information and form at least one command, one or more programmable data-plane engines (310, 320, 370) selectively operable for at least one of a plurality of cryptographic processes selectable in response to the at least one command, and a programmable host processor (100) coupled to such a data-plane engine (310) and such a control-plane engine (410). Other processors, circuits, devices and systems and processes for their operation and manufacture are disclosed.
    Type: Grant
    Filed: August 24, 2018
    Date of Patent: February 18, 2020
    Assignee: Texas Instruments Incorporated
    Inventors: Amritpal Singh Mundra, Denis Roland Beaudoin
  • Patent number: 10560428
    Abstract: A flexible hybrid firewall architecture that allows a mix of firewalls at end points in front of a target and at the initiator points. Groups of Priv-IDs may be created where each group is isolated from other worlds, with all firewalls controlled by a device management and security module.
    Type: Grant
    Filed: August 17, 2017
    Date of Patent: February 11, 2020
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Amritpal Singh Mundra, Brian J. Karguth, Timothy Anderson, Kai Chirca, Charles Fuoco
  • Publication number: 20200034572
    Abstract: A system-on-chip (SoC) is provided that includes security control registers, the security control registers including security flags for security critical assets of the SoC, wherein each security flag includes multiple bits.
    Type: Application
    Filed: July 30, 2018
    Publication date: January 30, 2020
    Inventor: Amritpal Singh Mundra
  • Publication number: 20190364018
    Abstract: In described examples, a system on a chip (SoC) and method for sending messages in the SoC include determining locations of initiator-side firewall block and receiver-side firewall block memories using respective pointers to the firewall block memories stored in a single, contiguous memory. Addresses of the pointers within the single memory depend on respective unique firewall identifiers of the firewall blocks. An exclusive security configuration controller uses the pointers to configure the firewall blocks over a security bus which is electrically isolated from a system bus. The system bus is used to send messages from sending functional blocks to receiving functional blocks. The initiator-side firewall block adds a message identifier to messages. The message identifier depends on the initiator-side firewall block's configuration settings.
    Type: Application
    Filed: December 14, 2018
    Publication date: November 28, 2019
    Inventors: Amritpal Singh Mundra, Chunhua Hu
  • Publication number: 20190362103
    Abstract: In described examples, a method of routing messages in a system on a chip (SoC) includes a secure message router receiving a message including a content, an identifier of the message's sending (origin) functional block and/or of a receiving (destination) functional block, a message secure value, a promote value, and a demote value. A context corresponding to the identifier is retrieved from a memory. The context includes an allow promote value and an allow demote value. The message secure value is increased if the promote value requests the increase and matches the allow promote value. The message secure value is decreased if the demote value requests the decrease and matches the allow demote value. Cleartext corresponding to the content is made accessible by the destination if the context secure value matches the message secure value. The message is then outputted from the secure message router to the destination.
    Type: Application
    Filed: December 14, 2018
    Publication date: November 28, 2019
    Inventors: Amritpal Singh Mundra, Eric Lasmana
  • Publication number: 20190058691
    Abstract: A flexible hybrid firewall architecture that allows a mix of firewalls at end points in front of a target and at the initiator points. Groups of Priv-IDs may be created where each group is isolated from other worlds, with all firewalls controlled by a device management and security module.
    Type: Application
    Filed: August 17, 2017
    Publication date: February 21, 2019
    Inventors: Amritpal Singh Mundra, Brian J. Karguth, Timothy Anderson, Kai Chirca, Charles Fuoco
  • Publication number: 20180367516
    Abstract: An electronic circuit (200) includes one or more programmable control-plane engines (410, 460) operable to process packet header information and form at least one command, one or more programmable data-plane engines (310, 320, 370) selectively operable for at least one of a plurality of cryptographic processes selectable in response to the at least one command, and a programmable host processor (100) coupled to such a data-plane engine (310) and such a control-plane engine (410). Other processors, circuits, devices and systems and processes for their operation and manufacture are disclosed.
    Type: Application
    Filed: August 24, 2018
    Publication date: December 20, 2018
    Inventors: Amritpal Singh Mundra, Denis Roland Beaudoin
  • Patent number: 10110573
    Abstract: An electronic circuit (200) includes one or more programmable control-plane engines (410, 460) operable to process packet header information and form at least one command, one or more programmable data-plane engines (310, 320, 370) selectively operable for at least one of a plurality of cryptographic processes selectable in response to the at least one command, and a programmable host processor (100) coupled to such a data-plane engine (310) and such a control-plane engine (410). Other processors, circuits, devices and systems and processes for their operation and manufacture are disclosed.
    Type: Grant
    Filed: October 9, 2017
    Date of Patent: October 23, 2018
    Assignee: Texas Instruments Incorporated
    Inventors: Amritpal Singh Mundra, Denis Roland Beaudoin
  • Publication number: 20180034790
    Abstract: An electronic circuit (200) includes one or more programmable control-plane engines (410, 460) operable to process packet header information and form at least one command, one or more programmable data-plane engines (310, 320, 370) selectively operable for at least one of a plurality of cryptographic processes selectable in response to the at least one command, and a programmable host processor (100) coupled to such a data-plane engine (310) and such a control-plane engine (410). Other processors, circuits, devices and systems and processes for their operation and manufacture are disclosed.
    Type: Application
    Filed: October 9, 2017
    Publication date: February 1, 2018
    Inventors: Amritpal Singh Mundra, Denis Roland Beaudoin
  • Publication number: 20170104732
    Abstract: An electronic circuit (200) includes one or more programmable control-plane engines (410, 460) operable to process packet header information and form at least one command, one or more programmable data-plane engines (310, 320, 370) selectively operable for at least one of a plurality of cryptographic processes selectable in response to the at least one command, and a programmable host processor (100) coupled to such a data-plane engine (310) and such a control-plane engine (410). Other processors, circuits, devices and systems and processes for their operation and manufacture are disclosed.
    Type: Application
    Filed: December 21, 2016
    Publication date: April 13, 2017
    Inventors: Amritpal Singh Mundra, Denis Roland Beaudoin
  • Publication number: 20170017943
    Abstract: A financial transaction system includes sensors, a tamper detection module, and circuitry configurable to control which sensors are used, and the circuitry is configurable after the tamper detection module has been manufactured.
    Type: Application
    Filed: July 14, 2015
    Publication date: January 19, 2017
    Inventors: Erkan Bilhan, Rajitha Padakanti, Amritpal Singh Mundra
  • Patent number: 9503265
    Abstract: An electronic circuit (200) includes one or more programmable control-plane engines (410, 460) operable to process packet header information and form at least one command, one or more programmable data-plane engines (310, 320, 370) selectively operable for at least one of a plurality of cryptographic processes selectable in response to the at least one command, and a programmable host processor (100) coupled to such a data-plane engine (310) and such a control-plane engine (410). Other processors, circuits, devices and systems and processes for their operation and manufacture are disclosed.
    Type: Grant
    Filed: February 17, 2016
    Date of Patent: November 22, 2016
    Assignee: Texas Instruments Incorporated
    Inventors: Amritpal Singh Mundra, Denis Roland Beaudoin
  • Publication number: 20160323253
    Abstract: An electronic circuit (200) includes one or more programmable control-plane engines (410, 460) operable to process packet header information and form at least one command, one or more programmable data-plane engines (310, 320, 370) selectively operable for at least one of a plurality of cryptographic processes selectable in response to the at least one command, and a programmable host processor (100) coupled to such a data-plane engine (310) and such a control-plane engine (410). Other processors, circuits, devices and systems and processes for their operation and manufacture are disclosed.
    Type: Application
    Filed: July 8, 2016
    Publication date: November 3, 2016
    Inventors: Amritpal Singh Mundra, Denis Roland Beaudoin
  • Publication number: 20160173283
    Abstract: An electronic circuit (200) includes one or more programmable control-plane engines (410, 460) operable to process packet header information and form at least one command, one or more programmable data-plane engines (310, 320, 370) selectively operable for at least one of a plurality of cryptographic processes selectable in response to the at least one command, and a programmable host processor (100) coupled to such a data-plane engine (310) and such a control-plane engine (410). Other processors, circuits, devices and systems and processes for their operation and manufacture are disclosed.
    Type: Application
    Filed: February 17, 2016
    Publication date: June 16, 2016
    Inventors: Amritpal Singh Mundra, Denis Roland Beaudoin
  • Patent number: 9305184
    Abstract: An electronic circuit (200) includes one or more programmable control-plane engines (410, 460) operable to process packet header information and form at least one command, one or more programmable data-plane engines (310, 320, 370) selectively operable for at least one of a plurality of cryptographic processes selectable in response to the at least one command, and a programmable host processor (100) coupled to such a data-plane engine (310) and such a control-plane engine (410). Other processors, circuits, devices and systems and processes for their operation and manufacture are disclosed.
    Type: Grant
    Filed: May 14, 2015
    Date of Patent: April 5, 2016
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Amritpal Singh Mundra, Denis Roland Beaudoin
  • Patent number: 9141831
    Abstract: An electronic circuit (200) includes one or more programmable control-plane engines (410, 460) operable to process packet header information and form at least one command, one or more programmable data-plane engines (310, 320, 370) selectively operable for at least one of a plurality of cryptographic processes selectable in response to the at least one command, and a programmable host processor (100) coupled to such a data-plane engine (310) and such a control-plane engine (410). Other processors, circuits, devices and systems and processes for their operation and manufacture are disclosed.
    Type: Grant
    Filed: June 21, 2011
    Date of Patent: September 22, 2015
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Amritpal Singh Mundra, Denis Roland Beaudoin
  • Publication number: 20150249654
    Abstract: An electronic circuit (200) includes one or more programmable control-plane engines (410, 460) operable to process packet header information and form at least one command, one or more programmable data-plane engines (310, 320, 370) selectively operable for at least one of a plurality of cryptographic processes selectable in response to the at least one command, and a programmable host processor (100) coupled to such a data-plane engine (310) and such a control-plane engine (410). Other processors, circuits, devices and systems and processes for their operation and manufacture are disclosed.
    Type: Application
    Filed: May 14, 2015
    Publication date: September 3, 2015
    Inventors: Amritpal Singh Mundra, Denis Roland Beaudoin
  • Publication number: 20130326131
    Abstract: A security context management system within a security accelerator that can operate with high latency memories and can provide line-rate processing on several security protocols. The method employed hides the memory latencies by having the processing engines working in a pipelined fashion. It is designed to auto-fetch security context from external memory, and will allow any number of simultaneous security connections by caching only limited contexts on-chip and fetching other contexts as needed. The module does the task of fetching and associating security context with ingress packet, and populates the security context RAM with data from the external memory.
    Type: Application
    Filed: May 29, 2012
    Publication date: December 5, 2013
    Applicant: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Amritpal Singh Mundra, Denis Beaudoin, Eric Lasmana
  • Publication number: 20120008768
    Abstract: An electronic data processing module (600) includes a context storage (640), cryptographic cores (615.i) adapted for acceleration of respective different types of encryption and decryption, and a mode control engine (610) responsive to a security context in said context storage (640) to operate one more selected said cryptographic cores according to a cryptographic mode at least partially specified by the security context. Other circuits and processes are also disclosed.
    Type: Application
    Filed: June 21, 2011
    Publication date: January 12, 2012
    Applicant: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Amritpal Singh Mundra, Eric Lasmana