Patents by Inventor Amulya Pandey

Amulya Pandey has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11835991
    Abstract: In an embodiment, a method for managing self-tests in an integrated circuit (IC) includes: receiving built-in-self-test (BIST) configuration data; configuring a first clock to a first frequency based on the BIST configuration data; performing a first BIST test at the first frequency; configuring a second clock to a second frequency that is different from the first frequency; and performing a second BIST test at the second frequency.
    Type: Grant
    Filed: March 22, 2021
    Date of Patent: December 5, 2023
    Assignee: STMicroelectronics International N.V.
    Inventors: Amulya Pandey, Balwinder Singh Soni, Amritanshu Anand, Venkata Narayanan Srinivasan
  • Patent number: 11698833
    Abstract: In an embodiment, an electronic circuit includes: a plurality of signal channels; a signal collection circuit configured to determine an action of the electronic circuit based on channel signals from the plurality of signal channels; and a first signal management circuit coupled between the plurality of signal channels and the signal collection circuit, the first signal management circuit including: a set of internal registers, a set of user registers, and a decoder configured to program the set of internal registers based on a content of the set of user registers, where the first signal management circuit is configured to receive the channel signals via the plurality of signal channels, generate first aggregated signals based on the received channel signals and a content of the set of internal registers, and transmitting the first aggregated signals to the signal collection circuit.
    Type: Grant
    Filed: January 3, 2022
    Date of Patent: July 11, 2023
    Assignee: STMICROELECTRONICS INTERNATIONAL N.V.
    Inventors: Amulya Pandey, Manish Bansal, Sandeep Bhattacharya
  • Publication number: 20230214292
    Abstract: In an embodiment, an electronic circuit includes: a plurality of signal channels; a signal collection circuit configured to determine an action of the electronic circuit based on channel signals from the plurality of signal channels; and a first signal management circuit coupled between the plurality of signal channels and the signal collection circuit, the first signal management circuit including: a set of internal registers, a set of user registers, and a decoder configured to program the set of internal registers based on a content of the set of user registers, where the first signal management circuit is configured to receive the channel signals via the plurality of signal channels, generate first aggregated signals based on the received channel signals and a content of the set of internal registers, and transmitting the first aggregated signals to the signal collection circuit.
    Type: Application
    Filed: January 3, 2022
    Publication date: July 6, 2023
    Inventors: Amulya Pandey, Manish Bansal, Sandeep Bhattacharya
  • Publication number: 20220300389
    Abstract: In an embodiment, a method for managing self-tests in an integrated circuit (IC) includes: receiving built-in-self-test (BIST) configuration data; configuring a first clock to a first frequency based on the BIST configuration data; performing a first BIST test at the first frequency; configuring a second clock to a second frequency that is different from the first frequency; and performing a second BIST test at the second frequency.
    Type: Application
    Filed: March 22, 2021
    Publication date: September 22, 2022
    Inventors: Amulya Pandey, Balwinder Singh Soni, Amritanshu Anand, Venkata Narayanan Srinivasan
  • Patent number: 11209482
    Abstract: A device for a system on a chip (SOC), the device includes: a comparator that includes a first input port, a second input port, and an output port. A first input signal and a second input signal are split into N bit pairs that include one bit from the first input signal and one bit from the second input signal. The comparator is configured so a mismatch between the first input signal and the second input signal causes an output signal to assume a first expected state. The device further comprises a test controller to perform a first operability test by mismatching the N bit pairs and verifying that the output signal assumes the first expected state.
    Type: Grant
    Filed: November 30, 2020
    Date of Patent: December 28, 2021
    Assignee: STMICROELECTRONICS INTERNATIONAL N.V.
    Inventors: Vivek Mohan Sharma, Deepak Baranwal, Amulya Pandey