Abstract: A microcontroller having error injection circuitry is provided. The microcontroller may include one or more operational components, and an error injection circuity operatively coupled to the one or more operational components. The error injection circuitry may autonomously inject one or more errors into the one or more operational components, and guard one or more error channels associated with the one or more operational components during the injection of the one or more errors.

Abstract: A system for processing signals from multiple analog-to-digital converters (ADCs) is provided. The system may include a first ADC to receive a first input signal and convert the first input signal to a first digital signal, a second ADC to obtain a second input signal and convert the second input signal to a second digital signal, a control logic circuitry to receive one or more configuration settings of the first ADC and apply the one or more configuration settings to the second ADC, and a computation logic circuitry to generate one or more computational results in response to comparing the first digital signal and the second digital signal.

Abstract: A serial communication apparatus is provided. The serial communication apparatus may include a transmitter to transmit data by outputting an output signal, and a collision detection circuitry operatively coupled to the transmitter to receive the output signal. The collision detection circuitry is to receive an input signal from an input buffer, compare the input signal and output signal, and provide a collision indication signal in response to a difference between the output signal and the input signal.

Abstract: A system for encoding and decoding in a communication protocol is provided, and may include a transmitter having a transmit data buffer to store a data, an encoding circuitry operatively coupled to the transmit data buffer to receive the data from the transmit data buffer and encode the data based on a selected encoding method, and a transmit shift register operatively coupled to the encoding circuitry to receive the encoded data and transmit the encoded data in the bitwise manner. The system may include a receiver having a receive shift register to receive the encoded data, a decoding circuitry operatively coupled to the receive shift register to receive the encoded data from the receive shift register in a parallel manner, and decode the encoded data based on a selected decoding method, and a receive data buffer operatively coupled to the decoding circuitry to receive the decoded data.

Abstract: Disclosed embodiments relate to sensing states and changes of states of a signal and sensors for the same, including but not limited to, autonomous sensors. Such sensor may include an analog signal threshold detection circuit, a state detection circuit, and a measurement circuit. The analog signal threshold detection circuit may be configured to alternately assert and de-assert a threshold detected indication in response to an input signal and a state thereof. The state detection circuit may be configured to generate a signal state indication about a state of the input signal. The measurement circuit may be configured to generate a measurement in response to assertions of the threshold detected indication and the signal state indication, such as a count, a slew rate, or a frequency. In some embodiments, disclosed sensors may have programmable thresholds for sensing the signal states and changes therein.

Abstract: A serial communication link receiver-transmitter with autonomous transmission error detection is described, and a communication peripherals including the same. Transmit data at a transmitter and transmitted data output by the transmitter and received by the receiver are observed by an error detector configured to generate an error indication in response to difference between the transmit data and corresponding observed transmit data of a transmitted data frame. If a difference is detected a transmit error indicator is asserted.

Abstract: Disclosed embodiments relate to sensing states and changes of states of a signal and sensors for the same, including but not limited to, autonomous sensors. Such sensor may include an analog signal threshold detection circuit, a state detection circuit, and a measurement circuit. The analog signal threshold detection circuit may be configured to alternately assert and de-assert a threshold detected indication in response to an input signal and a state thereof. The state detection circuit may be configured to generate a signal state indication about a state of the input signal. The measurement circuit may be configured to generate a measurement in response to assertions of the threshold detected indication and the signal state indication, such as a count, a slew rate, or a frequency. In some embodiments, disclosed sensors may have programmable thresholds for sensing the signal states and changes therein.

Abstract: Systems and methods described in this disclosure relate, generally, to analyzing electronic circuitry, and more specifically, to analyzing efficiency of clock gating in electronic circuitry. Analysis may include identifying wasted propagation of clock signals by clock gates and/or for a circuitry as a whole. In some embodiments, modified gating logic may be determined that improves clock gating efficiency, for example, by eliminating at least some wasted propagation of clock signals.

Abstract: A serial communication link receiver-transmitter with autonomous transmission error detection is described, and a communication peripherals including the same. Transmit data at a transmitter and transmitted data output by the transmitter and received by the receiver are observed by an error detector configured to generate an error indication in response to difference between the transmit data and corresponding observed transmit data of a transmitted data frame. If a difference is detected a transmit error indicator is asserted.

Abstract: Systems and methods described in this disclosure relate, generally, to analyzing electronic circuitry, and more specifically, to analyzing efficiency of clock gating in electronic circuitry. Analysis may include identifying wasted propagation of clock signals by clock gates and/or for a circuitry as a whole. In some embodiments, modified gating logic may be determined that improves clock gating efficiency, for example, by eliminating at least some wasted propagation of clock signals.