Patents by Inventor Amur GHOSE

Amur GHOSE has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Methods and systems for congestion prediction in logic synthesis using graph neural networks
    Patent number: 11675951
    Abstract: Method and system for assisting electronic chip design, comprising: receiving netlist data for a proposed electronic chip design, the netlist data including a list of circuit elements and a list of interconnections between the circuit elements; converting the netlist data to a graph that represents at least some of the circuit elements as nodes and represents the interconnections between the circuit elements as edges; extracting network embeddings for the nodes based on a graph topology represented by the edges; extracting degree features for the nodes based on the graph topology; and computing, using a graph neural network, a congestion prediction for the circuit elements that are represented as nodes based on the extracted network embeddings and the extracted degree features.
    Type: Grant
    Filed: May 28, 2021
    Date of Patent: June 13, 2023
    Assignee: HUAWEI TECHNOLOGIES CO., LTD.
    Inventors: Amur Ghose, Yingxue Zhang, Zhanguang Zhang
  • METHODS AND SYSTEMS FOR CONGESTION PREDICTION IN LOGIC SYNTHESIS USING GRAPH NEURAL NETWORKS
    Publication number: 20220405455
    Abstract: Method and system for assisting electronic chip design, comprising: receiving netlist data for a proposed electronic chip design, the netlist data including a list of circuit elements and a list of interconnections between the circuit elements; converting the netlist data to a graph that represents at least some of the circuit elements as nodes and represents the interconnections between the circuit elements as edges; extracting network embeddings for the nodes based on a graph topology represented by the edges; extracting degree features for the nodes based on the graph topology; and computing, using a graph neural network, a congestion prediction for the circuit elements that are represented as nodes based on the extracted network embeddings and the extracted degree features.
    Type: Application
    Filed: May 28, 2021
    Publication date: December 22, 2022
    Inventors: Amur GHOSE, Yingxue ZHANG, Zhanguang ZHANG