Abstract: All digital RF modulator. An RF modulator, implemented using only digital techniques, obviates the need for an additional board, implemented using discrete analog components, to perform the necessary modulation to provide the RF output signal for use with a display device (television). Modern displays typically include functionality to support a number of input types beyond an RF input. However, older, legacy displays typically only support inputs that are RF in nature. A fully integrated solution that performs the RF modulation of the output signal that may be used in such legacy types systems is provided using digital techniques.

Abstract: An integrated digital BTSC encoder with an improved pilot signal generator substantially implemented on a single CMOS integrated circuit. By digitally generating a sinusoid that is frequency locked to a two-state input reference signal using a high rate internal clock, a hardware-efficient BTSC pilot signal generator is provided with good acquisition and tracking performance. Implemented efficiently as a simple phase detector, a low-complexity loop filter, a pilot frequency offset adder, a phase accumulator and a sinusoidal generator, the invention enables lower-rate post-processing of the pilot tone without a costly variable interpolator decimator structures.

Abstract: An integrated digital BTSC encoder is implemented on a single CMOS integrated circuit chip with an all digital RF modulator. A set top box is provided that allows for a fully integrated solution which may be used with legacy television systems and also with other audio/visual equipment connected to the set top box.

Abstract: An BTSC encoder with an improved digital filter structure substantially implemented on a single CMOS integrated circuit is described. By cascading first and second order allpass filter structures to form a higher order digital filter, such as a Cauer low pass filter, limit cycle oscillations are reduced or eliminated, word-length growth from one stage to the next is contained, and a more efficient overall filter structure and performance is obtained.

Abstract: An integrated digital BTSC encoder with an improved pilot signal generator substantially implemented on a single CMOS integrated circuit. By digitally generating a sinusoid that is frequency locked to a two-state input reference signal using a high rate internal clock, a hardware-efficient BTSC pilot signal generator is provided with good acquisition and tracking performance. Implemented efficiently as a simple phase detector, a low-complexity loop filter, a pilot frequency offset adder, a phase accumulator and a sinusoidal generator, the invention enables lower-rate post-processing of the pilot tone without a costly variable interpolator decimator structures.

Abstract: An integrated digital BTSC encoder with an improved pilot signal generator substantially implemented on a single CMOS integrated circuit is described. By digitally generating a sinusoid that is frequency locked to a two-state input reference signal using a high rate internal clock, a hardware-efficient BTSC pilot signal generator is provided with good acquisition and tracking performance. Implemented efficiently as a simple phase detector, a low-complexity loop filter, a pilot frequency offset adder, a phase accumulator and a sinusoidal generator, the invention enables lower-rate post-processing of the pilot tone without a costly variable interpolator decimator structures.

Abstract: An integrated digital BTSC encoder substantially implemented on a single CMOS integrated circuit is described. By saturating and adding offsets to the value of the feedback control signal in regions of operation where the calculation for the control signal is dominated by noise, an integrated circuit selectively adjusts the control signal for the spectral or wideband feedback loop, as required, so that the performance of a very low noise digital BTSC encoder complies with the requirements of the BTSC standard.

Abstract: The present invention includes a method of determining a phase estimate for an input signal having pilot symbols. The method includes receiving a plurality of pilot symbols, and then multiplying two or more pilot symbol slots by corresponding correlator coefficients to correct a phase estimate of the input signal.

Abstract: A method and apparatus for the detection and correction of large carrier offsets. A set of known correction carrier offsets are used to translate an input signal having a carrier offset. After applying each correction carrier offset, a state of a timing recovery loop is evaluated. The set of known correction carrier offsets are sequentially used to translate the input signal until the timing recovery loop is locked. The carrier offset is substantially acquired when the timing recovery loop is locked.

Abstract: An update algorithm for equalizer coefficients in a communications system using phase correction symbols. Instead of using a traditional all symbols slicer update algorithm, the equalizer is updated during phase correction symbols for optimal performance in low signal-to-noise ratio conditions. In lower signal-to-noise ratio conditions, the equalizer uses a phase correction circuit to compensate for distortion caused by a communication channel when a demodulated data stream contains an unknown phase offsets resulting from a fast dynamic distortion. More specifically, the phase correction circuit uses a phase correction signal to correct for the unknown phase offsets in a demodulated data stream in lower signal-to-noise ratio conditions. The equalizer then corrects for distortion caused by the communication channel based upon the phase corrected demodulated data stream.

Abstract: A method and apparatus is disclosed for detecting the amount of unknown offset present in a received data stream. The unknown phase offset may offset the phase of the transmitted data stream from the received data stream. A phase detector uses a soft-decision slicer to estimate the content of a modulation transmitted data stream. The soft-decision slicer generates an estimate of the transmitted data stream depending on the location of the received data stream in relation to a transfer function of the soft-decision slicer depending on the modulation scheme of the received data stream. The phase detector uses the estimate of the transmitted data stream to calculate the amount of the unknown phase offset.

Abstract: An BTSC encoder with an improved digital filter structure substantially implemented on a single CMOS integrated circuit is described. By cascading first and second order allpass filter structures to form a higher order digital filter, such as a Cauer low pass filter, limit cycle oscillations are reduced or eliminated, word-length growth from one stage to the next is contained, and a more efficient overall filter structure and performance is obtained.

Abstract: An integrated digital BTSC encoder substantially implemented on a single CMOS integrated circuit is described. By incorporating a BTSC encoder within an all digital RF modulator, an improved set top box is provided, obviating the need for an additional BTSC encoder and modulator board and/or discrete analog components. A fully integrated solution that performs BTSC encoding within the RF modulator may be used with legacy television systems and also with other audio/visual equipment connected to the set top box.

Abstract: An integrated digital BTSC encoder with an improved pilot signal generator substantially implemented on a single CMOS integrated circuit is described. By digitally generating a sinusoid that is frequency locked to a two-state input reference signal using a high rate internal clock, a hardware-efficient BTSC pilot signal generator is provided with good acquisition and tracking performance. Implemented efficiently as a simple phase detector, a low-complexity loop filter, a pilot frequency offset adder, a phase accumulator and a sinusoidal generator, the invention enables lower-rate post-processing of the pilot tone without a costly variable interpolator decimator structures.

Abstract: An integrated digital BTSC encoder substantially implemented on a single CMOS integrated circuit is described. By saturating and adding offsets to the value of the feedback control signal in regions of operation where the calculation for the control signal is dominated by noise, an integrated circuit selectively adjusts the control signal for the spectral or wideband feedback loop, as required, so that the performance of a very low noise digital BTSC encoder complies with the requirements of the BTSC standard.