Patents by Inventor Amy M. Novak

Amy M. Novak has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Apparatus for testing embedded memory read paths
    Patent number: 7925937
    Abstract: An integrated circuit. The integrated circuit includes a plurality of logic circuits. The integrated circuit further includes a scan chain including a plurality of scan elements coupled in series, wherein the scan chain is configured to load stimulus data to be applied to the logic circuits for testing. The scan chain is further configured to capture data subsequent to applying the stimulus data. The integrated circuit also includes an embedded memory having a read port, wherein the read port is coupled to one or more of the plurality of logic circuits via a read path. The embedded memory includes a virtual entry having a plurality of scan-controllable storage elements. During testing, the virtual entry is operable to apply transition data to the read path in order to cause logic state transitions in the one or more logic circuits in the read path.
    Type: Grant
    Filed: January 7, 2008
    Date of Patent: April 12, 2011
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Joel T. Irby, Grady L. Giles, Alexander W. Schaefer, Gregory A. Constant, Floyd L. Dankert, Amy M. Novak
  • APPARATUS FOR TESTING EMBEDDED MEMORY READ PATHS
    Publication number: 20090177934
    Abstract: An integrated circuit. The integrated circuit includes a plurality of logic circuits. The integrated circuit further includes a scan chain including a plurality of scan elements coupled in series, wherein the scan chain is configured to load stimulus data to be applied to the logic circuits for testing. The scan chain is further configured to capture data subsequent to applying the stimulus data. The integrated circuit also includes an embedded memory having a read port, wherein the read port is coupled to one or more of the plurality of logic circuits via a read path. The embedded memory includes a virtual entry having a plurality of scan-controllable storage elements. During testing, the virtual entry is operable to apply transition data to the read path in order to cause logic state transitions in the one or more logic circuits in the read path.
    Type: Application
    Filed: January 7, 2008
    Publication date: July 9, 2009
    Inventors: Joel T. Irby, Grady L. Giles, Alexander W. Schaefer, Gregory A. Constant, Floyd D. Dankert, Amy M. Novak
  • Memory array with global bitline domino read/write scheme
    Patent number: 7355881
    Abstract: A circuit for implementing memory arrays using a global bitline domino read/write scheme. The memory circuit includes a plurality of cells each configured to store a bit of data. The memory circuit further includes a plurality of local bitlines, wherein each cells is coupled to one of the local bitlines. Each of the plurality of local bitlines is a differential bitline having a signal path and a complementary signal path which are cross-coupled by a pair of transistors.
    Type: Grant
    Filed: November 22, 2005
    Date of Patent: April 8, 2008
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Floyd L. Dankert, Victor F. Andrade, Randal L. Posey, Michael K. Ciraula, Alexander W. Schaefer, Jerry D. Moench, Soolin Kao Chrudimsky, Michael C. Braganza, Jan Michael Huber, Amy M. Novak