Abstract: The present invention relates to a reaction platform, which comprises: a machine body with a bottom plate for placing non-porous substrates; and a coater module configured on the top of the machine body and capable of maintaining a preset of a predetermined height for moving along the surface of non-porous substrate, wherein the coater module has one or more slits, and a target liquid can be directly injected or sucking in from the outside of the coater module through the slit, and spreading the target liquid onto a surface of the non-porous substrate while moving along the non-porous substrate; wherein the surface of the non-porous substrate has a target to be coated. The reaction platform of the present invention can not only save time, labor and cost, but also have accurate and reproducible experimental results, showing better results than traditional methods.

Abstract: A display device includes: a light emitting element; a first inorganic encapsulation layer disposed on the light emitting element to cover the light emitting element, and including a first encapsulation layer, a plasma treatment layer disposed on the first encapsulation layer, and a second encapsulation layer disposed on the plasma treatment layer; an organic encapsulation layer disposed on the first inorganic encapsulation layer; and a second inorganic encapsulation layer disposed on the organic encapsulation layer.

Abstract: A centrifugal fan for a heating, ventilation, air conditioning, and refrigeration (HVACR) system is disclosed. The centrifugal fan includes a volute housing having an inner surface and a curved inlet shroud. The volute housing defines an air outlet. The curved inlet shroud defines an air inlet. The air inlet has an inlet airflow cross-sectional area that lies substantially perpendicular to an outlet airflow cross-sectional area of the air outlet. The centrifugal fan also includes an impeller mounted for rotation about a rotational axis within the volute housing. The impeller has a plurality of fan blades. The plurality of fan blades has an outer surface. The centrifugal fan further includes a light source. The inner surface of the volute housing and the outer surface of the plurality of fan blades includes a photocatalyst layer. The light source is configured to emit light on the photocatalyst layer.

Abstract: A centrifugal fan for a heating, ventilation, air conditioning, and refrigeration (HVACR) system is disclosed. The centrifugal fan includes a volute housing having an inner surface and a curved inlet shroud. The volute housing defines an air outlet. The curved inlet shroud defines an air inlet. The air inlet has an inlet airflow cross-sectional area that lies substantially perpendicular to an outlet airflow cross-sectional area of the air outlet. The centrifugal fan also includes an impeller mounted for rotation about a rotational axis within the volute housing. The impeller has a plurality of fan blades. The plurality of fan blades has an outer surface. The centrifugal fan further includes a light source. The inner surface of the volute housing and the outer surface of the plurality of fan blades includes a photocatalyst layer. The light source is configured to emit light on the photocatalyst layer.

Abstract: The present disclosure provides a multi-substrate handling system having an alignment apparatus capable of positioning each of a set of substrates in predetermined orientations for transfer. A buffer chamber is configured to receive and condition the set of substrates which are disposed on a substrate carrier. A first transfer assembly is configured to transfer the set of substrates to and from the buffer chamber and is capable of transferring each of the set of substrates from the alignment apparatus to the carrier in the buffer chamber. The carrier includes a plurality of modules capable of securing the set of substrates. The system includes a second transfer assembly having at least two robots configured to transfer the carrier of the set of substrates between the buffer chamber and a process chamber. The process chamber is capable of processing the set of substrates using different process parameters for each substrate.

Abstract: In a method for semiconductor processing, a semiconductor substrate is provided. The semiconductor substrate defines at least one first trench therein. The at least one first trench has a first depth (d1). A coating layer is deposited onto the semiconductor substrate using at least one precursor under a setting for a processing temperature (T). The coating layer defines at least one second trench having a second depth (d2) above the at least one first trench. A first depth parameter (t) of the second depth (d2) relative to the first depth (d1) is determined. The processing temperature (T) is then determined based on the first depth parameter (t).

Abstract: A centrifugal fan for a heating, ventilation, air conditioning, and refrigeration (HVACR) system is disclosed. The centrifugal fan includes a volute housing having an inner surface and a curved inlet shroud. The volute housing defines an air outlet. The curved inlet shroud defines an air inlet. The air inlet has an inlet airflow cross-sectional area that lies substantially perpendicular to an outlet airflow cross-sectional area of the air outlet. The centrifugal fan also includes an impeller mounted for rotation about a rotational axis within the volute housing. The impeller has a plurality of fan blades. The plurality of fan blades has an outer surface. The centrifugal fan further includes a light source. The inner surface of the volute housing and the outer surface of the plurality of fan blades includes a photocatalyst layer. The light source is configured to emit light on the photocatalyst layer.

Abstract: In a method for semiconductor processing, a semiconductor substrate is provided. The semiconductor substrate defines at least one first trench therein. The at least one first trench has a first depth (d1). A coating layer is deposited onto the semiconductor substrate using at least one precursor under a setting for a processing temperature (T). The coating layer defines at least one second trench having a second depth (d2) above the at least one first trench. A first depth parameter (t) of the second depth (d2) relative to the first depth (d1) is determined. The processing temperature (T) is then determined based on the first depth parameter (t).

Abstract: In a method for semiconductor processing, a semiconductor substrate is provided. The semiconductor substrate defines at least one first trench therein. The at least one first trench has a first depth (d1). A coating layer is deposited onto the semiconductor substrate using at least one precursor under a setting for a processing temperature (T). The coating layer defines at least one second trench having a second depth (d2) above the at least one first trench. A first depth parameter (t) of the second depth (d2) relative to the first depth (d1) is determined. The processing temperature (T) is then determined based on the first depth parameter (t).

Abstract: In a method for semiconductor processing, a semiconductor substrate is provided. The semiconductor substrate defines at least one first trench therein. The at least one first trench has a first depth (d1). A coating layer is deposited onto the semiconductor substrate using at least one precursor under a setting for a processing temperature (T). The coating layer defines at least one second trench having a second depth (d2) above the at least one first trench. A first depth parameter (t) of the second depth (d2) relative to the first depth (d1) is determined. The processing temperature (T) is then determined based on the first depth parameter (t).

Abstract: In a method for semiconductor processing, a semiconductor substrate is provided. The semiconductor substrate defines at least one first trench therein. The at least one first trench has a first depth (d1). A coating layer is deposited onto the semiconductor substrate using at least one precursor under a setting for a processing temperature (T). The coating layer defines at least one second trench having a second depth (d2) above the at least one first trench. A depth parameter (t) the second depth (d2) relative to the first depth (d1) is determined. The processing temperature (T) is then determined based on a pre-determined standard reference curve comprising a plurality of references depth parameters in a first range as a function of a plurality of reference processing temperatures in a second range.

Abstract: In a method for semiconductor processing, a semiconductor substrate is provided. The semiconductor substrate defines at least one first trench therein. The at least one first trench has a first depth (d1). A coating layer is deposited onto the semiconductor substrate using at least one precursor under a setting for a processing temperature (T). The coating layer defines at least one second trench having a second depth (d2) above the at least one first trench. A depth parameter (t) the second depth (d2) relative to the first depth (d1) is determined. The processing temperature (T) is then determined based on a pre-determined standard reference curve comprising a plurality of references depth parameters in a first range as a function of a plurality of reference processing temperatures in a second range.

Abstract: A method for fabricating a shallow trench isolation includes forming a trench in a substrate, forming a bottom shallow trench isolation dielectric filling a gap of the trench, and forming a top shallow trench isolation dielectric on the bottom shallow trench isolation. The bottom shallow trench isolation dielectric has a concave center portion, and the top shallow trench isolation dielectric is deposited on the bottom shallow trench isolation by a high density plasma chemical vapor deposition process using low deposition to sputter ratio. A semiconductor structure having the shallow trench isolation is also disclosed.

Abstract: A semiconductor device includes a substrate, a gate stack, at least one epitaxy structure, a dielectric material, and a contact. The gate stack is present on the substrate. The gate spacer is present on a sidewall of the gate stack. The epitaxy structure is partially present in the substrate. The dielectric material is present on the substrate and between the epitaxy structure and the gate spacer. The contact is present on the epitaxy structure, the dielectric material, and the gate spacer.

Abstract: A method for fabricating a shallow trench isolation includes forming a trench in a substrate, forming a bottom shallow trench isolation dielectric filling a gap of the trench, and forming a top shallow trench isolation dielectric on the bottom shallow trench isolation. The bottom shallow trench isolation dielectric has a concave center portion, and the top shallow trench isolation dielectric is deposited on the bottom shallow trench isolation by a high density plasma chemical vapor deposition process using low deposition to sputter ratio. A semiconductor structure having the shallow trench isolation is also disclosed.

Abstract: A power switching circuit is connected to an external power source, a battery, and a load. The power switching circuit includes a voltage converter, a prevention unit, a detecting unit, and a switch. The voltage converter converts a first primary voltage supplied by the external power source to a secondary voltage. The prevention unit allows the secondary voltage to be transmitted to the load, the secondary voltage powering the load. The detecting unit generates a first level signal when the external power source fails to output the first primary voltage. The switch is turned on to transmit a second primary voltage supplied by the battery to the load and the prevention unit in response to the first level signal. The second primary voltage powers the load. The prevention unit prevents the second primary voltage from being transmitted to the voltage converter.

Abstract: A direct digital frequency synthesizer outputting a sine signal is disclosed, comprising an accumulator, a symmetry circuit, a coarse circuit, a fine circuit and a sign circuit, wherein the accumulator sequentially outputs a sample address according to a frequency control signal. The symmetry circuit takes the complement of the sample address according to a first clock, the period of the first clock being twice the period of the first MSB of the sample address, to obtain a symmetric sample address represented by N bits. The coarse circuit connected to the symmetry circuit outputs the first M MSBs of the symmetric sample address as the first M MSBs of the sine signal. The fine circuit predicts the last N-M LSBs of the sine signal from the last N-M LSBs of the symmetric sample address according to the first M MSBs of the symmetric sample address of the coarse circuit.