Abstract: Fin and nanostructured channel structure formation techniques for three-dimensional transistors can tune device performance. For example, fin profile control can be achieved by modifying the shape of fins/nanostructured channel structures so as to reduce their line edge roughness. Consequently, current flow within the channel regions of fins and nanostructured channel structures can be improved, enhancing device performance.

Abstract: An optical calibration tool includes a first body, a light emitter, a light receiver, a second body, and a light reflecting member. The first body has a first engaging port and a second engaging port. The light emitter and the light receiver are disposed in the first body. The second body has a third engaging port and a channel communicated with each other. The third engaging port is configured to selectively engage one of the first engaging port and the second engaging port. When the third engaging port is engaged with the first engaging port, the light emitter is optically coupled to the light reflecting member. When the third engaging port is engaged with the second engaging port, the light receiver is optically coupled to the light reflecting member.

Abstract: An electrical connector includes an insulating housing, a number of terminals and a lossy member. The terminals include a number of ground terminals and a number of signal terminals. The ground terminals and the signal terminals are set adjacently to each other but do not contact each other. The ground terminals do not directly contact the lossy member. As a result, installation consistency of the ground terminals can be achieved, thereby improving the electrical performance of the electrical connector.

Abstract: An interface connector, comprising a housing, a first heat dissipating member, and a second heat dissipating member. A first accommodating space and a second accommodating space are disposed in the housing. The first accommodating space is adjacent to the second accommodating space. The first accommodating space accommodates a first mating connector. The second accommodating space accommodates a second mating connector. The first heat dissipating member is disposed at the outside of the housing and passes through the housing. The first heat dissipating member extends into the first accommodating space to be connected to the first mating connector. The second heat dissipating member is disposed in the housing. The second heat dissipating member extends into the second accommodating space to be connected to the second mating connector.

Abstract: A method of fabricating a semiconductor device is described. A substrate is provided. A first semiconductor region of a first semiconductor material is formed over the substrate and adjacent a second semiconductor region of a second semiconductor material. The first and second semiconductor regions are crystalline. An etchant is selective to etch the first semiconductor region over the second semiconductor region. The entire first semiconductor region is implanted to form an amorphized semiconductor region. The amorphized semiconductor region is etched with the etchant using the second semiconductor region as a mask to remove the amorphized semiconductor region without removing the second semiconductor region.

Abstract: Touch sensitive display technologies (e.g., integrated touch-display pixel-based systems) are evolving to contain more analog and digital circuits inside the panel itself instead of the traditionally simple thin-film transistors. This improves the display characteristics but makes those circuits more vulnerable to the impact of external ESD strikes, which can degrade the user experience. This disclosure describes a series of circuits and techniques to mitigate the impact of these discharges on front of screen artifacts and potential false touches. These circuits and techniques may include: performing configuration-only panel updates independently of the image refresh rate, improving the in-panel memory circuits to make them resistant to unexpected pin toggles via disabling of a write path in response to a read clock, implementing a pin corruption detector and implementing a supply injection detector.

Abstract: Disclosed is a semiconductor device and semiconductor fabrication method. A semiconductor device includes: a substrate having a metal gate, gate spacers on sides of the metal gate, an etch stop layer (ESL), and interlayer dielectric (ILD) material over a source/drain region; a tungsten (W) cap formed from W material deposited over the metal gate and between the gate spacers; and a via gate (VG) formed above the W cap. A semiconductor fabrication method includes: receiving a substrate having a metal gate, gate spacers on sides of the metal gate, an etch stop layer (ESL), and interlayer dielectric (ILD) material over a source/drain region; depositing tungsten (W) material over the substrate; removing unwanted W material to form a W cap; and forming a via gate (VG) on the W cap.

Abstract: A method of forming a semiconductor device includes the following steps. A metal layer with at least one silicon-containing pattern therein is provided. A first wet etching process is performed by using a first etching solution, to clean a surface of the metal layer, wherein the first etching solution contains a base and a first oxidant. At least one cycle is performed. Each cycle includes a second wet etching process and a cleaning process. The second wet etching process is performed by using a second etching solution, to remove the metal layer, wherein the second etching solution contains an acid and a second oxidant. A cleaning process is performed.

Abstract: Disclosed is a method comprising: providing at least two structures with a metal layer over each; forming a patterned photolithographic layer over the metal layer over the first structure; removing the metal layer from the second structure via wet etch operations using a chemical etchant that is resistant to penetration into the photolithographic layer; and achieving, after wet etch operations, a remaining metal ratio of a distance X over a distance Y that is less than 179 and greater than 1, wherein X is the distance from a first line extending from an edge of the metal layer over the first structure to a second line extending from an edge of a channel region in the second structure, and Y is a second distance from the first line to a third line extending from an edge of the metal layer formed over the channel region in the first structure.

Abstract: Disclosed is a semiconductor device and semiconductor fabrication method. A semiconductor device includes: a gate structure over a semiconductor substrate, having a low-k dielectric layer, a high-k dielectric layer, a p-type work function metal layer, an n-type work function metal layer, a silicon oxide scap layer, and a glue layer; and a continuous tungsten (W) cap over the gate structure that was formed by the gate structure being pretreated, W material being deposited and etched back, the scap layer being etched, additional W material being deposited, and unwanted W material being removed. A semiconductor fabrication method includes: receiving a gate structure; pretreating the gate structure; depositing W material on the gate structure; etching back the W material; etching the scap layer; depositing additional W material; and removing unwanted W material.

Abstract: A semiconductor device includes a plurality of fin structures disposed over a substrate and a work function alloy layer disposed over each fin structure of the plurality of fin structures. The plurality of fin structures includes a first fin structure and a second fin structure. A content of a first element in a first portion of the work function alloy layer, which portion is disposed over the first fin structure, is different from a content of the first element in a second portion of the work function alloy layer, which portion is disposed over the second fin structure.

Abstract: A method includes forming a gate stack, which includes a first portion over a portion of a first semiconductor fin, a second portion over a portion of a second semiconductor fin, and a third portion connecting the first portion to the second portion. An anisotropic etching is performed on the third portion of the gate stack to form an opening between the first portion and the second portion. A footing portion of the third portion remains after the anisotropic etching. The method further includes performing an isotropic etching to remove a metal gate portion of the footing portion, and filling the opening with a dielectric material.

Abstract: A method of fabricating a semiconductor device is described. A substrate is provided. A first semiconductor region of a first semiconductor material is formed over the substrate and adjacent a second semiconductor region of a second semiconductor material. The first and second semiconductor regions are crystalline. An etchant is selective to etch the first semiconductor region over the second semiconductor region. The entire first semiconductor region is implanted to form an amorphized semiconductor region. The amorphized semiconductor region is etched with the etchant using the second semiconductor region as a mask to remove the amorphized semiconductor region without removing the second semiconductor region.

Abstract: A method for making a middle-of-line interconnect structure in a semiconductor device includes forming, near a surface of a first interconnect structure comprised of a first metal, a region of varied composition including the first metal and a second element. The method further includes forming a recess within the region of varied composition. The recess laterally extends a first distance along the surface and vertically extends a second distance below the first surface. The method further includes filling the recess with a second metal to form a second interconnect structure that contacts the first interconnect structure.

Abstract: A semiconductor structure includes a semiconductor substrate, a dielectric layer, a tungsten plug, a conductive plug, and a contact barrier. The dielectric layer is over a semiconductor substrate. The tungsten plug is in the dielectric layer. The conductive plug is on the tungsten plug. The contact barrier includes a sidewall barrier on a sidewall of the conductive plug and a bottom barrier between the conductive plug and the tungsten plug. A thickness of the sidewall barrier is greater than a thickness of the bottom barrier.

Abstract: A modular and electromechanically integrated easy-entry mechanism includes an easy-entry mechanism, manufactured independently of slide rail assemblies, and mounted on upper slide rails in the slide rail assemblies by fasteners. A total travel of slide rails is divided into a comfort travel for front-rear adjustment of a passenger and an easy-entry travel for increasing an easy-entry/exit space for a passenger in the third row seating. The unlocking of the slide rails is mechanically maintained in the easy-entry travel, and the slide rails are ensured to be locked at the front-most position of the comfort travel when a seat is retracted. The easy-entry mechanism is driven manually or by electric power, and acts independently on unlocking pins in slide rail locking mechanisms to unlock the slide rail assemblies. The easy-entry mechanism is modularly designed, easy to manufacture, mount, and replace, and does not affect the existing slide rail manufacturing process.

Abstract: An electrical connector, comprising a housing, a first upper terminal module, a second upper terminal module, a first lower terminal module, and a second lower terminal module. The first upper terminal module, the second upper terminal module, the first lower terminal module, and the second lower terminal module respectively comprise an insulating body, a plurality of signal terminals, a plurality of ground terminals, and an electromagnetic shielding member. The plurality of signal terminals and the plurality of ground terminals are disposed in the insulating body. A plurality of signal terminals are disposed between two adjacent ground terminals. The plurality of first ground terminals respectively comprise a plurality of flat contacting parts exposed from the insulating body, where the heights of the plurality of flat contacting parts of respective ground terminals are different. The electromagnetic shielding member is disposed on the insulating body.

Abstract: A method includes forming isolation regions extending into a semiconductor substrate. A semiconductor strip is between the isolation regions. The method further includes recessing the isolation regions so that a top portion of the semiconductor strip protrudes higher than top surfaces of the isolation regions to form a semiconductor fin, measuring a fin width of the semiconductor fin, generating an etch recipe based on the fin width, and performing a thinning process on the semiconductor fin using the etching recipe.

Abstract: A method for making a middle-of-line interconnect structure in a semiconductor device includes forming, near a surface of a first interconnect structure comprised of a first metal, a region of varied composition including the first metal and a second element. The method further includes forming a recess within the region of varied composition. The recess laterally extends a first distance along the surface and vertically extends a second distance below the first surface. The method further includes filling the recess with a second metal to form a second interconnect structure that contacts the first interconnect structure.

Abstract: Described here are delivery devices for delivering one or more implants to the body, and methods of using. The delivery devices may deliver implants to a variety of locations within the body, for a number of different uses. In some variations, the delivery devices have a cannula with one or more curved sections. In some variations, a pusher may be used to release one or more implants from the cannula. In some variations, one or more of the released implants may be a self-expanding device. Methods of delivering implants to one or more sinus cavities are also described here.