Abstract: A method of determining color composition of an image includes calculating an intensity value and a saturation value for each pixel of the image, comparing the calculated intensity and saturation values for each pixel with first and second predetermined threshold values, respectively, and labeling pixels with calculated intensity values above the first predetermined threshold value and calculated saturation values above the second predetermined threshold value as color pixels. Next, a mask is applied to the image and the number of color pixels selected by the mask is counted. If the number of color pixels selected by the mask is greater than or equal to a predetermined density value, the image is determined to be a color image.

Abstract: A coating apparatus (20) for forming a photoresist film on a substrate (21) includes a flat table (30), a nozzle unit (40), and a particle cleaning unit (50). The flat table is used for supporting the substrate. The nozzle unit is used for dispensing photoresist material on a top surface of the substrate. The particle cleaning unit is used for removing particles from the top surface before the photoresist material is coated thereon. The coating apparatus can timely clean the substrate before coating. The coating performance is improved, and the nozzle unit is protected from being scratched or damaged.

Abstract: A device includes a plurality of luminance adjustment tables, a luminance analysis unit for analyzing a luminance distribution of a plurality of pixels of a source video, and a dynamic luminance curve fitting unit electrically connected to the luminance analysis unit and the luminance adjustment tables for adjusting luminance levels of the pixels of the video based on one of the luminance adjustment tables selected according to the luminance distribution.

Abstract: An I/O circuit placement method. In the I/O circuit placement method, at least two rows of I/O circuits are placed on a first side of the chip, and each I/O circuit has a head section and a tail section. The placement direction of the head section and the tail section is perpendicular to the placement direction of the I/O circuits in the rows. The semiconductor further has a core circuit disposed on the chip, wherein the rows of I/O circuits are disposed outside the core circuit and are at the periphery of the chip. Due to the I/O circuit placement in the semiconductor device, the present invention reduces the area of the semiconductor chip and fabrication cost.

Abstract: A mux scan cell includes a multiplexer having a first input node for receiving raw data, a second input node for receiving test data, an output node, a selection node, and a delay circuit electrically connected between the second input node and the output node for prolonging a traveling time which the test data takes to travel from the second input node to the output node. The mux scan cell also includes a flip-flop connected to the multiplexer. With the delay circuit, the traveling time of the test data is prolonged such that the traveling time which the test data takes to travel from the second input node to the output node simulates a sum of a traveling time in which the raw data travels through a combinational logic and a traveling time in which the raw data travels from the first input node to the output node.

Abstract: A method for correcting faded colors in aged photographs or film. The method automatically restores the color of the image by analyzing the color variance in the image and determining tonal curve for each channel. First, the interior of the image is selected and the image is portioned into sub-images. The variance of each sub-image is calculated, and the parameters are evaluated for correcting the entire image during scanning. This method will provide good color quality and preserve good density of the image.

Abstract: A method of forecasting a unit capacitance of a chip having a plurality of layers. Each layer includes a predetermined layout of metal lines. First, layout design parameters of the predetermined layout are obtained before forming the chip, such as number of layout layers, metal line width of each layout layer, distance between each metal line and the ratio of metal lines to routing channels. Next, a testing interconnection according to the layout design parameters is generated. Finally, the unit capacitance is obtained by a predetermined capacitance extraction tool according to the testing interconnection.

Abstract: A memory test system for peak power reduction. The memory test system includes a plurality of memories, a plurality of memory built-in self-test circuits and a plurality of delay units. Each of the memory built-in self-test circuits comprises a built-in self-test controller for receiving a clock signal and producing a plurality of required control signals to test one of the memories. Each of the delay units is coupled between two adjacent built-in self-test controllers. The clock signal input to one of the built-in self-test controllers is received by the delay unit to produce a delayed clock signal, and the delay unit outputs the delayed clock signal to the other.

Abstract: A mux scan cell includes a multiplexer having a first input node for receiving raw data, a second input node for receiving test data, an output node, a selection node, and a delay circuit electrically connected between the second input node and the output node for prolonging a traveling time which the test data takes to travel from the second input node to the output node. The mux scan cell also includes a flip-flop connected to the multiplexer. With the delay circuit, the traveling time of the test data is prolonged such that the traveling time which the test data takes to travel from the second input node to the output node simulates a sum of a traveling time in which the raw data travels through a combinational logic and a traveling time in which the raw data travels from the first input node to the output node.

Abstract: A silicon chip capacitance measurement circuit including three pairs of completely matched MOS transistors divided into two symmetrical circuits. Capacitance of a capacitor within the silicon chip is measured using the difference in average charging current flowing from the measurement circuit via a left and a right capacitor. A power supply provides a constant voltage source to the measurement circuit. A current measuring device measures the current flowing from the power supply to the measurement circuit. A signal generator provides a group of three-phase non-overlapping signals to the measurement circuit. The capacitance measurement circuit is able to limit measurement error due to the return of different size negative currents leading to the transient switching of MOS transistors in the current measurement device so that accuracy of capacitance measurement improves.

Abstract: A clock architecture including a clock source, a multi-phase clock signal generator, a control bus, a number of clock signal lines, and at least one circuit block. The clock source generates a global clock signal, which is then transferred to the multi-phase clock signal generator connected to the clock source. Upon receipt of global clock signal, the multi-phase clock signal generator, which is connected to a control bus, generates clock signals of different phases according to the signals from the control bus. Each of the clock signal branches transfers one of the clock signals of different phases, wherein each of the clock signal branches is individually connected to the circuit block through an electrical switch. Only one switch is at an on state at one time, so that the clock signal of a corresponding phase is transferred to the circuit block. The driving forces applied on the clock buffer connected to the clock source and the clock buffers on the branches are adjustable for reducing clock skew.

Abstract: A lampshade consists of a foldable frame, a shade attached on the frame, and a mounting fitting detachably fitted with the frame. The mounting fitting is formed by bending a steel wire to have an upper portion consisting of a pair of laterally extending ears and a pair of vertical extending portions, a lower portion consisting a pair of pear-shaped gripping portions. The upper portion is used to engage with the frame, and the lower portion is used to engage with an incandescent bulb of a lamp so that the lampshade can be mounted onto the lamp.

Abstract: A smoking composition is provided which comprises a smoking material and, as a source of flavor or aroma for the smoke thereof, certain aromatic beta-hydroxy compounds. Compounds which may be employed as a source of flavor or aroma include beta-hydroxy esters formed by condensing, using a Reformatsky-type reaction, an alkyl alpha-bromo-isobutyrate or homolog thereof with an aromatic aldehyde such as benzaldehyde, anisaldehyde or piperonal. Other compounds which may be employed are the acids and/or metal salts which are formed by hydrolysis of such beta-hydroxy esters.