Patents by Inventor An Chen

An Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10268519
    Abstract: A scheduling method is provided. The method includes: recording a next instruction and a ready state of each thread group in a scoreboard; determining whether there is any ready thread group whose ready state is affirmative; determining whether a load/store unit is available, wherein the load/store unit is configured to access a data memory unit; when the load/store unit is available, determining whether the ready thread groups include a data access thread group, wherein the next instruction of the data access thread group is related to accessing the data memory unit; selecting a target thread group from the data access thread groups; and dispatching the target thread group to the load/store unit for execution.
    Type: Grant
    Filed: December 29, 2015
    Date of Patent: April 23, 2019
    Assignee: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
    Inventors: Heng-Yi Chen, Chung-Ho Chen, Chen-Chieh Wang, Juin-Ming Lu, Chun-Hung Lai, Hsun-Lun Huang
  • Patent number: 10269737
    Abstract: A method of manufacturing a semiconductor structure include: providing a die including a die pad disposed over the die; disposing a conductive member over the die pad of the die; forming a molding surrounding the die and the conductive member; disposing a dielectric layer over the molding, the die and the conductive member; and forming an interconnect structure including a land portion and a plurality of via portions. The land portion is disposed over the dielectric layer, the plurality of via portions are disposed over the conductive member and protruded from the land portion to the conductive member through the dielectric layer, and each of the plurality of via portions at least partially contacts with the conductive member.
    Type: Grant
    Filed: October 6, 2017
    Date of Patent: April 23, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Chang-Pin Huang, Hsien-Ming Tu, Ching-Jung Yang, Shih-Wei Liang, Hung-Yi Kuo, Yu-Chia Lai, Hao-Yi Tsai, Chung-Shi Liu, Chen-Hua Yu
  • Patent number: 10269752
    Abstract: Package structures and methods of forming package structures are discussed. A package structure, in accordance with some embodiments, includes an integrated circuit die, an encapsulant at least laterally encapsulating the integrated circuit die, a redistribution structure on the integrated circuit die and the encapsulant, a connector support metallization coupled to the redistribution structure, and an external connector on the connector support metallization. The redistribution structure includes a dielectric layer disposed distally from the encapsulant and the integrated circuit die. The connector support metallization has a first portion on a surface of the dielectric layer and has a second portion extending in an opening through the dielectric layer. The first portion of the connector support metallization has a sloped sidewall extending in a direction away from the surface of the dielectric layer.
    Type: Grant
    Filed: January 26, 2015
    Date of Patent: April 23, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chen-Hua Yu, Chien-Yu Li, Hung-Jui Kuo, Li-Hsien Huang, Hsien-Wei Chen, Der-Chyang Yeh, Chung-Shi Liu, Shin-Puu Jeng
  • Patent number: 10269949
    Abstract: A semiconductor structure includes: a channel layer; an active layer over the channel layer, wherein the active layer is configured to form a two-dimensional electron gas (2DEG) to be formed in the channel layer along an interface between the channel layer and the active layer; a gate electrode over a top surface of the active layer; and a source/drain electrode over the top surface of the active layer; wherein the active layer includes a first layer and a second layer sequentially disposed therein from the top surface to a bottom surface of the active layer, and the first layer possesses a higher aluminum (Al) atom concentration compared to the second layer. An HEMT structure and an associated method are also disclosed.
    Type: Grant
    Filed: October 27, 2017
    Date of Patent: April 23, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Yao-Chung Chang, Po-Chih Chen, Jiun-Lei Jerry Yu, Chun Lin Tsai
  • Patent number: 10267954
    Abstract: A near eye display device and method are provided. The near eye display device including: a display panel and a lens module. The display panel includes a plurality of display areas arranged in an array, each of the display areas includes at least one pixel unit; and the lens module includes a plurality of micro-lenses arranged in an array, which include a plurality of deflection micro-lenses, an end of the deflection micro-lenses close to a center of the lens module is closer to the display panel than an end of the deflection micro-lenses far away from the center of the lens module, each of the display areas corresponds to at least one of the micro-lenses, and an adjacent portion of two adjacent display areas of the display areas corresponds to two different micro-lenses of the micro-lenses, and the two different micro-lenses include at least one of the deflection micro-lenses.
    Type: Grant
    Filed: March 29, 2017
    Date of Patent: April 23, 2019
    Assignee: BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Can Wang, Yafeng Yang, Jian Gao, Can Zhang, Xinli Ma, Wei Wang, Jifeng Tan, Xiaochuan Chen
  • Patent number: 10270824
    Abstract: A computer-implemented method, computer program product, and computing system for providing a live stream of event content is provided. In an embodiment, a method may include defining an online collaborative space associated with an event. A plurality of event participants may be associated with the event. Content contributions may be received from one or more of the event participants. An event content update may be transmitted to a client event application based on the received content contributions to provide a live stream of event content.
    Type: Grant
    Filed: April 23, 2018
    Date of Patent: April 23, 2019
    Assignee: Google LLC
    Inventors: Zachary Yeskel, Anton Lopyrev, Tianxuan Chen, Dave Cohen, Kavi Harshawat, Matthew Steiner, James Gallagher, Denise Ho, Ajmal Asver
  • Patent number: 10266523
    Abstract: The present disclosure relates to novel crystalline forms of N-[6-(cis-2,6-dimethylmorpholine-4-yl)pyridine-3-yl]-2-methyl-4?-(trifluoromethoxy) [1,1?-biphenyl]-3-carboxamide monophosphate, and process of preparation thereof. The crystalline form of the monophosphate of a compound of formula (I) has low hygroscopicity, is convenient to store, has better stability than that of diphosphonate in prior art, can avoid the risk of crystal transformation in the development and production of the drug. The preparation method is simple, has low cost, and has important value for further optimization and development of the drug.
    Type: Grant
    Filed: March 30, 2016
    Date of Patent: April 23, 2019
    Assignee: CRYSTAL PHARMATECH CO., LTD.
    Inventors: Minhua Chen, Yanfeng Zhang, Fei Lu, Xiaoyu Zhang
  • Patent number: 10268304
    Abstract: The present disclosure provides a touch display panel including a self-capacitance or mutual-capacitance type touch display panel, a manufacturing method and a method driving for the same and a display device. The self-capacitance type touch display panel includes an array substrate having a first metal layer and self-capacitance touch electrodes, and a touch control chip. Each touch electrode includes common electrodes, first metal layer includes touch lead wires corresponding to the touch electrodes, and each touch electrode is connected with the touch control chip via a corresponding touch lead wire. The touch lead wire is configured to transmit a common electrode signal to the touch electrode during a display stage, to transmit a touch scan signal to the touch electrode during a touch stage, and to transmit a touch signal, which is generated by the touch electrode at a position where a touch operation occurs, to the touch control chip.
    Type: Grant
    Filed: October 14, 2015
    Date of Patent: April 23, 2019
    Assignees: BOE TECHNOLOGY GROUP CO., LTD., BEIJING BOE OPTOELECTRONICS TECHNOLOGY CO., LTD.
    Inventors: Lei Wang, Xiaochuan Chen, Haisheng Wang, Shengji Yang, Rui Xu, Qian Wang, Changfeng Li, Ming Yang, Pengcheng Lu, Xiaoliang Ding, Wei Liu, Hongjuan Liu, Yingming Liu, Weijie Zhao, Zhenhua Lv, Shijun Wang
  • Patent number: 10266658
    Abstract: Crosslinked aminosiloxanes obtainable by reaction of identical or different aminosiloxanes with identical or different epoxide components which are water-soluble hydrocarbons, the hydrocarbons comprising oxygen as well as carbon, and optionally further elements selected from nitrogen, sulphur and phosphorus, the hydrocarbon having on average more than one terminal epoxy group, the epoxy group being a carbooxirane radical, and, further, not more than 50% of all the amino groups having undergone reaction with an epoxide group.
    Type: Grant
    Filed: February 28, 2015
    Date of Patent: April 23, 2019
    Assignee: EVONIK DEGUSSA GMBH
    Inventors: Frauke Henning, Jörg Peggau, Andrea Lohse, Ulrike Mahring, Fuming Chen
  • Patent number: 10269732
    Abstract: In some embodiments, a semiconductor package includes a die surrounded by a molding material, a redistribution layer over the die and the molding material, the redistribution layer electrically coupled to the die, and a first conductive structure in the molding material and electrically coupled to the die, the first conductive structure being an inductor or an antenna.
    Type: Grant
    Filed: October 3, 2016
    Date of Patent: April 23, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chen-Hua Yu, Chuei-Tang Wang
  • Patent number: 10269586
    Abstract: A semiconductor device includes a first die having a first active surface and a first backside surface opposite the first active surface, a second die having a second active surface and a second backside surface opposite the second active surface, and an interposer, the first active surface of the first die being electrically coupled to a first side of the interposer, the second active surface of the second die being electrically coupled to a second side of the interposer. The semiconductor device also includes a first connector over the interposer, a first encapsulating material surrounding the second die, the first encapsulating material having a first surface over the interposer, and a via electrically coupling the first connector and the interposer. A first end of the via is substantially coplanar with the first surface of the first encapsulating material.
    Type: Grant
    Filed: February 13, 2015
    Date of Patent: April 23, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Bruce C. S. Chou, Chih-Hsien Lin, Hsiang-Tai Lu, Jung-Kuo Tu, Tung-Hung Hsieh, Chen-Hua Lin, Mingo Liu
  • Patent number: 10270648
    Abstract: A method for managing configuration information is disclosed including: an operation support system (OSS)/network management system/(NMS) receiving a lifecycle operation completion message of a virtualized network function (VNF); and sending a management information object instance operation request message corresponding to a lifecycle operation of the VNF to an element management system (EMS) according to the received lifecycle operation completion message of the VNF. A method and device for managing configuration information, an element management system (EMS) and a storage medium are also disclosed.
    Type: Grant
    Filed: November 13, 2014
    Date of Patent: April 23, 2019
    Assignee: ZTE Corporation
    Inventor: Liping Chen
  • Patent number: 10269439
    Abstract: A storage device with a charge trapping (CT) based memory may include improved data retention performance. Data retention problems, such as charge loss in CT memory may increase for a particular programmed state when a neighboring state is at erased state. Modifying the erase state with post write erase conditioning (PWEC) by pushing up deeply erased states can reduce the lateral charge movement and improve high temperature data retention. In particular, the erase state may be reprogrammed such that the erase distribution is tighter with a higher voltage.
    Type: Grant
    Filed: March 28, 2017
    Date of Patent: April 23, 2019
    Assignee: Western Digital Technologies, Inc.
    Inventors: Mohan Vamsi Dunga, Changyuan Chen, Biswajit Ray
  • Patent number: 10265532
    Abstract: A system and method for selecting leadwire stimulation parameters includes a processor iteratively performing, for each of a plurality of values for a particular stimulation parameter, each value corresponding to a respective current field: (a) shifting the current field longitudinally and/or rotationally to a respective plurality of locations about the leadwire; and (b) for each of the respective plurality of locations, obtaining clinical effect information regarding a respective stimulation of the patient tissue produced by the respective current field at the respective location; and displaying a graph plotting the clinical effect information against values for the particular stimulation parameter and locations about the leadwire, and/or based on the obtained clinical effect information, identifying an optimal combination of a selected value for the particular stimulation parameter and selected location about the leadwire at which to perform a stimulation using the selected value.
    Type: Grant
    Filed: May 29, 2018
    Date of Patent: April 23, 2019
    Assignee: BOSTON SCIENTIFIC NEUROMODULATION CORPORATION
    Inventors: Stephen Carcieri, Dean Chen, Michael A. Moffitt
  • Patent number: 10269982
    Abstract: In a method for manufacturing a metallic-channel device, a metallic layer is formed on a substrate. The metallic layer is formed by an atomic layer deposition technique and has a first thickness. An insulating layer is formed over the metallic layer. A gate contact layer is formed over the insulating layer. The formed layers are processed to remove the gate contact layer, the insulating layer, and a portion of the metallic layer from a source-drain region. A remaining portion of the metallic layer on the source-drain region has a second thickness that is smaller than the first thickness. Source and drain metal contacts are formed over the remaining portion of the metallic layer.
    Type: Grant
    Filed: July 8, 2016
    Date of Patent: April 23, 2019
    Assignees: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., NATIONAL TAIWAN UNIVERSITY
    Inventors: Miin-Jang Chen, Chi-Wen Liu, Po-Hsien Cheng
  • Patent number: 10271182
    Abstract: A method, device and a computer program product operable in a communications network to provide enhanced public warning system (PWS+) messages to a communication device over the current PWS system is disclosed. The method includes generating, at a server or network device, at least one public warning system (PWS) message and at least one enhanced PWS (PWS+) message, and associating the PWS+ message with the at least one PWS message. The at least one PWS+ message and the PWS message are transmitted via a communications network to the communication device.
    Type: Grant
    Filed: July 29, 2015
    Date of Patent: April 23, 2019
    Assignee: BlackBerry Limited
    Inventors: John David Netto, Shu-Lin Chen, Michael Eoin Buckley
  • Patent number: 10267990
    Abstract: In an embodiment, a method includes: forming an interconnect including waveguides and conductive features disposed in a plurality of dielectric layers, the conductive features including conductive lines and vias, the waveguides formed of a first material having a first refractive index, the dielectric layers formed of a second material having a second refractive index less than the first refractive index; bonding a plurality of dies to a first side of the interconnect, the dies electrically connected by the conductive features, the dies optically connected by the waveguides; and forming a plurality of conductive connectors on a second side of the interconnect, the conductive connectors electrically connected to the dies by the conductive features.
    Type: Grant
    Filed: November 30, 2018
    Date of Patent: April 23, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chen-Hua Yu, Chuei-Tang Wang, Hsing-Kuo Hsia, Yu-Kuang Liao, Chih-Chieh Chang
  • Patent number: 10265499
    Abstract: A urinary catheter system includes a catheter, a sheath, an enclosure and a plug. The catheter has distal and proximal ends. The sheath is slidable along the catheter between first and second positions. The enclosure encloses a majority of the catheter and includes a bottom member, a top member, an outer peripheral wall defining an outer hole to allow advancement of the distal end, and an inner peripheral wall defining an inner hole, where the catheter is extendable through the inner hole. Rotating the top or bottom member relative to the other member causes the catheter to wind within the enclosure. The plug can seal the proximal end to block liquid flow, and a user can disengage the plug to allow liquid flow.
    Type: Grant
    Filed: September 17, 2015
    Date of Patent: April 23, 2019
    Assignee: COMPACTCATH, INC.
    Inventors: Daniel Wei-Chen Hong, Naama Stauber
  • Patent number: 10269787
    Abstract: Methods for cutting (e.g., dividing) metal gate structures in semiconductor device structures are provided. A dual layer structure can form sub-metal gate structures in a replacement gate manufacturing processes, in some examples. In an example, a semiconductor device includes a plurality of metal gate structures disposed in an interlayer dielectric (ILD) layer disposed on a substrate, an isolation structure disposed between the metal gate structures, wherein the ILD layer circumscribes a perimeter of the isolation structure, and a dielectric structure disposed between the ILD layer and the isolation structure.
    Type: Grant
    Filed: November 10, 2017
    Date of Patent: April 23, 2019
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Shiang-Bau Wang, Ming-Ching Chang, Shu-Yuan Ku, Ryan Chia-Jen Chen
  • Patent number: 10268019
    Abstract: Present embodiments provide for an optical imaging lens. The optical imaging lens includes a first lens element, a second lens element, a third lens element, a fourth lens element, a fifth lens element and a sixth lens element positioned in an order from an object side to an image side. Through controlling the convex or concave shape of the surfaces of the lens elements and designing parameters satisfying at least two inequalities, the optical imaging lens shows better optical characteristics, increases the effective focal length and narrows the angle of view while the total length of the optical imaging lens is shortened.
    Type: Grant
    Filed: October 7, 2016
    Date of Patent: April 23, 2019
    Assignee: GENIUS ELECTRONIC OPTICAL (XIAMEN) CO., LTD.
    Inventors: Feng Chen, Guangyun Li, Yanbin Chen