Abstract: A hub directly driven by a motor and used for a heavy-duty chassis dynamometer includes a hub body, wherein a mounting surface is arranged on an inner circumference of the hub body and is disposed around a transmission shaft coaxial with the hub body, the transmission shaft is sleeved with a driving assembly, and bearing assemblies are disposed on two sides of the driving assembly in an axial direction respectively; a plurality of axial mounting plates are disposed on an outer circumference of the driving assembly, and tension sensor assemblies are connected to the axial mounting plates located outside the hub body and are mounted on the support frame; and an end, away from the mounting surface, of the transmission shaft, is sleeved with an end flange plate, and a plurality of brake assemblies are disposed on the end flange plate and are mounted on the support frame.

Abstract: A semiconductor device includes a first transistor and a protection structure. The first transistor includes a gate electrode, a gate dielectric disposed on the gate electrode, and a channel layer disposed on the gate dielectric. The protection structure is laterally surrounding the gate electrode, the gate dielectric and the channel layer of the first transistor. The protection structure includes a first capping layer and a dielectric portion. The first capping layer is laterally surrounding and contacting the gate electrode, the gate dielectric and the channel layer of the first transistor. The dielectric portion is disposed on the first capping layer and laterally surrounding the first transistor.

Abstract: A bonding structure that may be used to form 3D-IC devices is formed using first oblong bonding pads on a first substrate and second oblong bonding pads one a second substrate. The first and second oblong bonding pads are laid crosswise, and the bond is formed. Viewed in a first cross-section, the first bonding pad is wider than the second bonding pad. Viewed in a second cross-section at a right angle to the first, the second bonding pad is wider than the first bonding pad. Making the bonding pads oblong and angling them relative to one another reduces variations in bonding area due to shifts in alignment between the first substrate and the second substrate. The oblong shape in a suitable orientation may also be used to reduce capacitive coupling between one of the bonding pads and nearby wires.

Abstract: A display panel includes a gate electrode, a source electrode, a drain electrode, and a metal oxide layer disposed corresponding to the gate electrode. The metal oxide layer includes a lower metal oxide layer and an upper metal oxide layer stacked on the lower metal oxide layer. The lower metal oxide layer includes an indium oxide and a lanthanoid oxide. The upper metal oxide layer is located on a surface of the lower metal oxide layer adjacent to the source electrode and the drain electrode. The source electrode and the drain electrode are connected to the upper metal oxide layer. The upper metal oxide layer includes an indium oxide and a lanthanoid oxide, and the upper metal oxide layer includes polycrystalline phase.

Abstract: This disclosure relates to a combined power module that includes a base structure, a terminal structure, a second terminal, and a cover. The terminal structure includes a mount assembly and a plurality of first terminals. The mount assembly is assembled on the base structure. The first terminals are disposed on the mount assembly. The second terminal is disposed on the base structure. The cover is disposed on the base structure and covers at least part of the first terminals and at least part of the second terminal.

Abstract: A substrate processing apparatus comprises a chamber member that defines an interior volume that has an aspect ratio. The chamber member comprises a pair of laterally opposing inlet walls and a loading port. Each of the pair of laterally opposing inlet walls has an inlet port configured to receive output from a remote plasma source. The loading port is arranged between the pair of inlet walls, configured to allow passage of a substrate into the interior volume.

Abstract: A low-carbon and low alloy hot-work die steel with a high toughness at low temperatures and a high strength at high temperatures and a high hardenability, comprises the following components: C: 0.15-0.35%, Si: 0.40-0.90%, Mn: ?0.80%, Cr: 1.50-2.40%, Ni: 2.50-4.50%, Mo: 1.00-1.60%, V: 0.10-0.40%, W: 0.20-0.90%, P: ?0.02%, S?0.02%, and a balance of Fe matrix and other inevitable impurities. The above percentages are mass percentages. The material of the present invention can have a V notch impact energy of 30 J or more than 30 J at ?40° C., a high temperature strength of 380 MPa or more at 700° C., and a hardenability of 200 mm or more to ensure the consistency of internal and external microstructures. The materials of the present invention can be applied to hot-work molds used in special working conditions that require high toughness at low temperatures, high strength at high temperatures and high hardenability.

Abstract: A method of performing air pollution estimation is provided. The method is to be implemented using a processor of a computer device and includes: generating a spectral image based on an original color image of an environment under test using a spectral transformation matrix; supplying the spectral image as an input into an estimating model for air pollution estimation; and obtaining an estimation result from the estimating model indicating a degree of air pollution of the environment under test.

Abstract: A semiconductor device structure is provided. The device includes one or more first semiconductor layers, each first semiconductor layer of the one or more first semiconductor layers is surrounded by a first intermixed layer, wherein the first intermixed layer comprises a first material and a second material.

Abstract: Bonded wafer device structures, such as a wafer-on-wafer (WoW) structures, and methods of fabricating bonded wafer device structures, including an array of contact pads formed in an interconnect level of at least one wafer of the bonded wafer device structure. The array of contact pads formed in an interconnect level of at least one wafer may have an array pattern that corresponds to an array pattern of contact pads that is subsequently formed over a surface of the bonded wafer structure. The array of contact pads formed in an interconnect level of at least one wafer of the bonded wafer device structure may enable improved testing of individual wafers, including circuit probe testing, prior to the wafer being stacked and bonded to one or more additional wafers to form a bonded wafer structure.

Abstract: A 3D display system and a 3D display method are provided. The 3D display system includes a 3D display, a memory, and a processor. The processor is coupled to the 3D display and the memory and is configured to execute the following steps. As a first type application program is executed, an image content of the first type application program is captured, and a stereo format image is generated according to the image content of the first type application program. The stereo format image is delivered to a runtime complying with a specific development standard through an application program interface complying with the specific development standard. A display frame processing associated with the 3D display is performed on the stereo format image through the runtime, and a 3D display image content generated by the display frame processing is provided to the 3D display for displaying.

Abstract: A method of forming a semiconductor device includes: forming a fin protruding above a substrate, where a top portion of the fin comprises a layer stack that includes alternating layers of a first semiconductor material and a second semiconductor material; forming a dummy gate structure over the fin; forming openings in the fin on opposing sides of the dummy gate structure; forming source/drain regions in the openings; removing the dummy gate structure to expose the first semiconductor material and the second semiconductor material under the dummy gate structure; performing a first etching process to selectively remove the exposed first semiconductor material, where after the first etching process, the exposed second semiconductor material form nanostructures, where each of the nanostructures has a first shape; and after the first etching process, performing a second etching process to reshape each of the nanostructures into a second shape different from the first shape.

Abstract: A container feeding device includes a casing and first and second latch members. The casing defines a lower retaining space for receiving a plurality of containers that are stacked on one another. The first latch member is operable to enter the lower retaining space for supporting a bottommost container, or leave the lower retaining space to release the bottommost container. The second latch member enters the lower retaining space to support a second bottommost container when the bottommost container is released by the first latch member.

Abstract: A heavy-duty, high-power and large-torque chassis dynamometer for a multi-environmental system, comprising a power testing platform disposed on the ground and a rack located below the power testing platform. A fixed base and a sliding base are sequentially disposed on an inner side of the rack in a length direction of the power testing platform, a pair of first hub assemblies are mounted on the fixed base through a plurality of support frames, a sliding platform is disposed on the sliding base, and a pair of second hub assemblies are mounted on the sliding platform through a plurality of support frames. Tension sensor assemblies are connected to outer circumferences of the first hub assemblies and outer circumferences of the second hub assemblies, and are fixedly disposed on the support frames.

Abstract: A semiconductor device structure, along with methods of forming such, are described. The semiconductor device structure includes a first dielectric feature extending along a first direction, the first dielectric feature comprising a first dielectric layer having a first sidewall and a second sidewall opposing the first sidewall, a first semiconductor layer disposed adjacent the first sidewall, the first semiconductor layer extending along a second direction perpendicular to the first direction, a second dielectric feature extending along the first direction, the second dielectric feature disposed adjacent the first semiconductor layer, and a first gate electrode layer surrounding at least three surfaces of the first semiconductor layer, and a portion of the first gate electrode layer is exposed to a first air gap.

Abstract: An electronic device includes a substrate, a plurality of flexible circuit boards, a plurality of ICs and an insulator. The flexible circuit boards are disposed on the substrate. In a top view of the electronic device, the flexible circuit boards are overlapped with an edge of the substrate. The ICs are disposed on the substrate. The insulator is disposed on the flexible circuit boards and contacted the ICs, wherein the insulator has a first side and a second side opposite to the first side and the first side is closer to the edge than the second side. Along a first direction perpendicular to an extension direction of the edge, a first minimum distance between the second side and one of the ICs is less than a second minimum distance between the second side and one of the flexible circuit boards.

Abstract: A tool set includes a tool holder, a tool and a tool rack. The tool has a groove unit. The tool holder has a latch unit that engages the groove unit. The tool rack includes a rack body and a blocking member. When the tool holder is moved away from the rack body after the tool is moved into the rack body by the tool holder and after the blocking member moves to a blocking position, the tool is blocked by the blocking member so that the latch unit is separated from the groove unit and that the tool holder is separated from the tool.

Abstract: The present disclosure provides a method for treating liver cirrhosis by using a composition including mesenchymal stem cells, extracellular vesicles produced by the mesenchymal stem cells, and growth factors. The composition of the present disclosure achieves the effect of treating liver cirrhosis through various efficacy experiments.

Abstract: A memory device and a method of operating a memory device are disclosed. In one aspect, the memory device includes a plurality of non-volatile memory cells, each of the plurality of non-volatile memory cells is operatively coupled to a word line, a gate control line, and a bit line. Each of the plurality of non-volatile memory cells comprises a first transistor, a second transistor, a first diode-connected transistor, and a capacitor. The first transistor, second transistor, first diode-connected transistor are coupled in series, with the capacitor having a first terminal connected to a common node between the first diode-connected transistor and the second transistor.

Abstract: A light-emitting device, including a first type semiconductor layer, a patterned insulating layer, a light-emitting layer, and a second type semiconductor layer, is provided. The patterned insulating layer covers the first type semiconductor layer and has a plurality of insulating openings. The insulating openings are separated from each other. The light-emitting layer is located in the plurality of insulating openings and covers a portion of the first type semiconductor layer. The second type semiconductor layer is located on the light-emitting layer.