Patents by Inventor An-Chi Chang

An-Chi Chang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240411122
    Abstract: A system and method for image-guided microscopic illumination are provided. A processing module controls an imaging assembly such that a camera acquires an image or images of a sample in multiple fields of view, and the image or images are automatically transmitted to a processing module and processed by the first processing module automatically in real-time based on a predefined criterion so as to determine coordinate information of an interested region in each field of view. The processing module also controls an illuminating assembly to illuminate the interested region of the sample according to the received coordinate information regarding to the interested region, with the illumination patterns changing among the fields of view.
    Type: Application
    Filed: August 21, 2024
    Publication date: December 12, 2024
    Inventors: Jung-Chi LIAO, Yi-De CHEN, Chih-Wei CHANG, Weng Man CHONG
  • Publication number: 20240412704
    Abstract: The present disclosure provides a method for driving a cholesteric liquid crystal display device. The method includes the following steps: utilizing a driving circuit section to sequentially activate each scanning electrode within a display panel; utilizing the driving circuit section to apply first alternating-current (AC) voltage pulses to pixel circuits on an activated scanning electrode during a first stage within a pulse-width modulation (PWM) scanning procedure of an activated scanning electrode; and utilizing the driving circuit section to apply second AC voltage pulses to the pixel circuits on the activated scanning electrode during a second stage of the PWM scanning procedure. A first voltage amplitude and a first period of the first AC voltage pulses are different from a second voltage amplitude and a second period of the second AC voltage pulses, respectively.
    Type: Application
    Filed: April 10, 2024
    Publication date: December 12, 2024
    Inventors: Hui Cheng LIN, Cheng-Hong YAO, Chi Chang LIAO
  • Publication number: 20240408055
    Abstract: The present invention relates to a use of a natural compound Anisomelic acid extracted from Anisomeles indica O. Kuntze in the preparation of pharmaceutical compositions for inhibiting the infection and replication of novel coronaviruses and the mutant strains (SARS-CoV-2 variants) thereof, the Anisomelic acid is a compound comprising a chemical structural Formula I, the pharmaceutical composition includes a safe and effective amount of Anisomelic acid, that is, the pharmaceutical composition is a combination of a safe and effective amount of Anisomelic acid and its pharmaceutically acceptable salt or carrier thereof.
    Type: Application
    Filed: October 21, 2021
    Publication date: December 12, 2024
    Applicants: Peking University Shenzhen Graduate School, CNS BIOTEK CORP., Gansu Evergreen Pharmaceuticals Co.,Ltd.
    Inventors: Zhen Yang, Yew-Min Tzeng, Jun-Min Quan, Qing Chang, Chi-Tai Yeh
  • Publication number: 20240413268
    Abstract: A semiconductor device includes a semiconductor stack, a reflective structure, and a conductive structure. The semiconductor stack includes a first semiconductor structure, a second semiconductor structure and an active region located between the first semiconductor structure and the second semiconductor structure. The reflective structure is located at a side of semiconductor stack closed to the first semiconductor structure, and includes a first metal. The conductive structure locates between the reflective structure and the first semiconductor structure, and includes a first region overlapping with the active structure and a second region which does not overlap with the active structure. The first metal in the second region has a concentration smaller than 5 atomic percent.
    Type: Application
    Filed: June 7, 2024
    Publication date: December 12, 2024
    Inventors: Yi-Yang CHIU, Chun-Yu LIN, Chun Wei CHANG, Yi-Ming CHEN, Chen OU, Hung-Yu CHOU, Liang-Yi WU, Hsiao-Chi YANG
  • Publication number: 20240411191
    Abstract: A double-layer cholesteric liquid crystal display and its manufacturing method are disclosed. The double-layer cholesteric liquid crystal display includes three transparent substrates, two opposing electrode layers, two cholesteric liquid crystal layers, and a first light-absorbing layer. Additionally, the double-layer cholesteric liquid crystal display incorporates two drive ICs and a second light-absorbing layer. The two drive ICs can be positioned either on the same side or on opposite sides within the non-display area of the double-layer cholesteric liquid crystal display. Furthermore, the first cholesteric liquid crystal layer exhibits a first color light, and the second cholesteric liquid crystal layer exhibits a second color light, where the colors are selected as contrasting colors. Additionally, the two cholesteric liquid crystal layers possess mutually opposite optical rotary properties.
    Type: Application
    Filed: June 3, 2024
    Publication date: December 12, 2024
    Inventors: CHENG-YU LIN, CHENG-HONG YAO, CHI-CHANG LIAO
  • Publication number: 20240408729
    Abstract: A cap feeding device is for a nap nailer that includes a machine body, a muzzle, a nail feeding device, a nail striking device, and an electronic control device. The cap feeding device includes a cartridge, a cap rail, a cap solenoid valve, and a cap pushing member. The cartridge is adapted for accommodating a plurality of caps. The cap rail is connected to the cartridge, and extends toward the muzzle. The cap solenoid valve is mounted to the cap rail, and includes a valve rod that is drivable by an electromagnetic force to move. The cap pushing member is swingably connected to the valve rod, and is urged by the valve rod to move relative to the muzzle between a first position, in which the cap pushing member is adjacent to the muzzle, and a second position, in which the cap pushing member is distal from the muzzle.
    Type: Application
    Filed: May 31, 2024
    Publication date: December 12, 2024
    Applicant: BASSO INDUSTRY CORP.
    Inventors: Sheng-Man WANG, Liang-Chi HUNG, Li-Hsin CHANG, Cheng-En TSAI
  • Publication number: 20240411450
    Abstract: A method for performing storage space management of a memory device with aid of dynamic block configuration includes: configuring at least one portion of blocks among a plurality of blocks to be multiple first blocks in a first region and multiple second blocks in a second region according to a first reserved block threshold; combining the multiple first blocks into a set of first superblocks in the first region; and combining at least one portion of second blocks among the multiple second blocks into a set of second superblocks in the second region, wherein the first reserved block threshold is less than a minimum non-damaged block count among respective non-damaged block counts of a plurality planes, for a memory controller to increase available storage capacity by increasing a ratio of a size of the second region to a size of the first region.
    Type: Application
    Filed: May 19, 2024
    Publication date: December 12, 2024
    Applicant: Silicon Motion, Inc.
    Inventors: Chin-Chun Chang, Sheng-Jui Wang, Ling-Chi Hsu
  • Patent number: 12166095
    Abstract: Methods for tuning effective work functions of gate electrodes in semiconductor devices and semiconductor devices formed by the same are disclosed. In an embodiment, a semiconductor device includes a channel region over a semiconductor substrate; a gate dielectric layer over the channel region; and a gate electrode over the gate dielectric layer, the gate electrode including a first work function metal layer over the gate dielectric layer, the first work function metal layer including aluminum (Al); a first work function tuning layer over the first work function metal layer, the first work function tuning layer including aluminum tungsten (AlW); and a fill material over the first work function tuning layer.
    Type: Grant
    Filed: November 30, 2023
    Date of Patent: December 10, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Hsin-Yi Lee, Cheng-Lung Hung, Weng Chang, Chi On Chui
  • Patent number: 12166074
    Abstract: A method includes removing a first dummy gate stack and a second dummy gate stack to form a first trench and a second trench. The first dummy gate stack and the second dummy gate stack are in a first device region and a second device region, respectively. The method further includes depositing a first gate dielectric layer and a second gate dielectric layer extending into the first trench and the second trench, respectively, forming a fluorine-containing layer comprising a first portion over the first gate dielectric layer, and a second portion over the second gate dielectric layer, removing the second portion, performing an annealing process to diffuse fluorine in the first portion into the first gate dielectric layer, and at a time after the annealing process, forming a first work-function layer and a second work-function layer over the first gate dielectric layer and the second gate dielectric layer, respectively.
    Type: Grant
    Filed: February 21, 2022
    Date of Patent: December 10, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Hsin-Yi Lee, Weng Chang, Hsiang-Pi Chang, Huang-Lin Chao, Chung-Liang Cheng, Chi On Chui, Kun-Yu Lee, Tzer-Min Shen, Yen-Tien Tung, Chun-I Wu
  • Patent number: 12166122
    Abstract: A memory device structure includes a transistor structure including a gate electrode over a top surface of a fin and adjacent to a sidewall of the fin, a source structure coupled to a first region of the fin and a drain structure coupled to a second region of the fin, where the gate electrode is between the first and the second region. A gate dielectric layer is between the fin and the gate electrode. The memory device structure further includes a capacitor coupled with the transistor structure, the capacitor includes the gate electrode, a ferroelectric layer on a substantially planar uppermost surface of the gate electrode and a word line on the ferroelectric layer.
    Type: Grant
    Filed: December 23, 2020
    Date of Patent: December 10, 2024
    Assignee: Intel Corporation
    Inventors: Shriram Shivaraman, Uygar Avci, Ashish Verma Penumatcha, Nazila Haratipour, Seung Hoon Sung, Sou-Chi Chang
  • Patent number: 12167611
    Abstract: In some embodiments, the present disclosure relates to a method of forming an integrated chip including forming a ferroelectric layer over a bottom electrode layer, forming a top electrode layer over the ferroelectric layer, performing a first removal process to remove peripheral portions of the bottom electrode layer, the ferroelectric layer, and the top electrode layer, and performing a second removal process using a second etch that is selective to the bottom electrode layer and the top electrode layer to remove portions of the bottom electrode layer and the top electrode layer, so that after the second removal process the ferroelectric layer has a surface that protrudes past a surface of the bottom electrode layer and the top electrode layer.
    Type: Grant
    Filed: July 24, 2023
    Date of Patent: December 10, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chih-Hsiang Chang, Kuo-Chi Tu, Sheng-Hung Shih, Wen-Ting Chu, Tzu-Yu Chen, Fu-Chen Chang
  • Patent number: 12166092
    Abstract: A device includes a substrate, an isolation structure over the substrate, a gate structure over the isolation structure, a gate spacer on a sidewall of the gate structure, a source/drain (S/D) region adjacent to the gate spacer, a silicide on the S/D region, a dielectric liner over a sidewall of the gate spacer and on a top surface of the isolation structure, wherein a bottom surface of the dielectric liner is above a top surface of the silicide layer and spaced away from the top surface of the silicide layer in a cross-sectional plane perpendicular to a lengthwise direction of the gate structure.
    Type: Grant
    Filed: June 5, 2023
    Date of Patent: December 10, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Lin-Yu Huang, Li-Zhen Yu, Chia-Hao Chang, Cheng-Chi Chuang, Yu-Ming Lin, Chih-Hao Wang
  • Publication number: 20240404882
    Abstract: Embodiments of the present disclosure provide semiconductor devices having conductive features with reduced height and increased width, and methods for forming the semiconductor devices. Particularly, sacrificial self-aligned contact (SAC) layer and sacrificial metal contact etch stop layer (M-CESL) are used to form conductive features with reduced resistance. After formation of the conductive features, the sacrificial SAC and sacrificial M-CESL are removed and replaced with a low-k material to reduce capacitance in the device. As a result, performance of the device is improved.
    Type: Application
    Filed: May 27, 2024
    Publication date: December 5, 2024
    Inventors: Sheng-Tsung WANG, Chia-Hao CHANG, Lin-Yu HUANG, Cheng-Chi CHUANG, Chih-Hao WANG
  • Publication number: 20240403939
    Abstract: A service platform using natural language for communication includes a request module, a natural language communication system and a product/service module. The request module is provided for a user to make a request in natural language. After receiving a request from a user, the natural language communication system converts and analyzes the request to obtain an analysis result. The product/service module provides a corresponding product or service according to the analysis result.
    Type: Application
    Filed: May 30, 2024
    Publication date: December 5, 2024
    Inventor: An-Chi CHANG
  • Publication number: 20240405123
    Abstract: A high-voltage device structure and methods of forming the same are described. In some embodiments, the structure includes a deep well region of a first conductivity type disposed in a substrate, a doped region disposed on the deep well region; a well region of the first conductivity type surrounding the deep well region and the doped region; a source region disposed on the well region, a drain region disposed on the doped region, and a first pickup region of the first conductivity type disposed on the well region. The first pickup region is laterally in contact with the source region, and the first pickup region, the well region, and the deep well region are electrically connected.
    Type: Application
    Filed: June 5, 2023
    Publication date: December 5, 2024
    Inventors: Chien-Ming KU, Wei-Jen CHANG, Wen-Hsing HSIEH, Ming-Yang HSU, Chia-Chi HO, Chung-Shih CHIANG
  • Publication number: 20240405658
    Abstract: A power supply device and an operation method thereof are provided. The power supply device includes a charge pump circuit and a power supply circuit. The power supply circuit supplies a first power voltage to the charge pump circuit. The charge pump circuit converts the first power voltage into a second power voltage so as to supply the second power voltage to an application circuit. The power supply circuit detects the second power voltage or an output current output by the charge pump circuit to obtain a detection result. The power supply circuit dynamically adjusts the first power voltage based on the detection result.
    Type: Application
    Filed: May 29, 2023
    Publication date: December 5, 2024
    Applicant: Novatek Microelectronics Corp.
    Inventors: Tuo-Kuang Chen, Jui-Chi Chang, Yi-Meng Lan, Yi-Chun Lee
  • Publication number: 20240401898
    Abstract: An arrow chain structure includes an arrow chain body and an extension member. The arrow chain body has a base part, the base part has an arrow groove and a pivoting member disposed on a side thereof, the pivoting member has an accommodation groove formed on a side thereof corresponding to the other side of the arrow groove. The extension member is disposed on the arrow chain body. The arrow chain bodies can be pivotally connected to each other by the pivoting members.
    Type: Application
    Filed: June 2, 2023
    Publication date: December 5, 2024
    Inventor: Chi-Chang Liu
  • Patent number: 12159916
    Abstract: A method for fabricating a semiconductor component includes forming an interlayer dielectric (ILD) layer on a substrate, forming a trench in the interlayer dielectric layer, forming a metal gate in the trench, removing a portion of the metal gate protruding from the ILD layer, reacting a reducing gas with the metal gate, and removing a top portion of the metal gate.
    Type: Grant
    Filed: July 25, 2023
    Date of Patent: December 3, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Po-Chi Wu, Chai-Wei Chang, Jung-Jui Li, Ya-Lan Chang, Yi-Cheng Chao
  • Publication number: 20240395562
    Abstract: Methods of manufacturing a chemical-mechanical polishing (CMP) slurry and methods of performing CMP process on a substrate comprising metal features are described herein. The CMP slurry may be manufactured using a balanced concentration ratio of chelator additives to inhibitor additives, the ratio being determined based on an electro potential (Ev) value of a metal material of the substrate. The CMP process may be performed on the substrate based on the balanced concentration ratio of chelator additives to inhibitor additives of the CMP slurry.
    Type: Application
    Filed: July 31, 2024
    Publication date: November 28, 2024
    Inventors: Chun-Hao Kung, Tung-Kai Chen, Chih-Chieh Chang, Kao-Feng Liao, Hui-Chi Huang, Kei-Wei Chen
  • Publication number: 20240393519
    Abstract: A front light guide plate and a reflective display are provided. The reflective display includes a front light guide plate, a light source and a display device, and the front light guide plate includes a first surface and a second surface corresponding to the first surface. A first surface includes a plurality of optical structures. Each optical structure includes a first optical surface, and a second optical surface disposed with the first optical surface in face-to-face fashion. The light source is implemented on the side of the front light guide plate, and the display device is provided with a second surface. When the light beams from the light source are reflected by the first optical surface of the front light guide plate and enter the display device, portion of the light beams emitted from the first optical surface to the second optical surface will be absorbed or scattered by the light reducing layer.
    Type: Application
    Filed: July 25, 2023
    Publication date: November 28, 2024
    Inventors: CHENG-YU LIN, CHENG-HUNG YAO, CHI-CHANG LIAO