Patents by Inventor An-Chi CHENG

An-Chi CHENG has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12009407
    Abstract: A method of forming a semiconductor device includes: forming a dummy gate structure over a nanostructure, where the nanostructure overlies a fin that protrudes above a substrate, where the nanostructure comprises alternating layers of a first semiconductor material and a second semiconductor material; forming openings in the nanostructure on opposing sides of the dummy gate structure, the openings exposing end portions of the first semiconductor material and end portions of the second semiconductor material; recessing the exposed end portions of the first semiconductor material to form first sidewall recesses; filling the first sidewall recesses with a multi-layer spacer film; removing at least one sublayer of the multi-layer spacer film to form second sidewall recesses; and forming source/drain regions in the openings after removing at least one sublayer, where the source/drain regions seal the second sidewall recesses to form sealed air gaps.
    Type: Grant
    Filed: April 20, 2023
    Date of Patent: June 11, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Wen-Kai Lin, Yung-Cheng Lu, Che-Hao Chang, Chi On Chui
  • Patent number: 12002719
    Abstract: A method includes patterning a trench and depositing a first insulating material along sidewalls and a bottom surface of the trench using a conformal deposition process. Depositing the first insulating material includes forming a first seam between a first portion of the first insulating material on a first sidewall of the trench and a second portion of the first insulating material on a second sidewall of the trench. The method further includes etching the first insulating material below a top of the trench and depositing a second insulating material over the first insulating material and in the trench using a conformal deposition process. Depositing the second insulating material comprises forming a second seam between a first portion of the second insulating material on the first sidewall of the trench and a second portion of the second insulating material on a second sidewall of the trench.
    Type: Grant
    Filed: December 19, 2022
    Date of Patent: June 4, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Sung-En Lin, Chi On Chui, Fang-Yi Liao, Chunyao Wang, Yung-Cheng Lu
  • Patent number: 12001616
    Abstract: A mouse device includes a lateral pressure sensing unit and a base unit having a base seat, a housing, and an inner space cooperatively defined by the base seat and the housing. The base seat is elongated in a front-rear direction, and includes a bottom face portion and an extension face portion surrounding and extending upwardly from the bottom face portion, and having spaced apart first and second lateral sections. The housing surrounds the base seat, extends upwardly from the extension face portion, and includes an operating portion extending upwardly from the first lateral section and having front, rear, upper, and lower pressing regions. The lateral pressure sensing unit is located in the inner space, is adjacent to the front, rear, upper and lower pressing regions, and is triggered upon operation on the operating portion.
    Type: Grant
    Filed: August 11, 2023
    Date of Patent: June 4, 2024
    Assignee: SUNREX TECHNOLOGY CORP.
    Inventors: Chun-Chieh Chen, Che-Hsun Chang, Chi-Shu Hsu, Chang-Cheng Lee
  • Publication number: 20240173819
    Abstract: A wafer grinding parameter optimization method and an electronic device are provided. The method includes the following. A natural frequency of a grinding wheel spindle of wafer processing equipment is obtained, and a grinding stability lobe diagram is generated accordingly. A grinding speed is selected based on a speed range of the grinding wheel spindle. Multiple grinding parameter combinations are determined based on the grinding speed. Multiple grinding simulation result combinations corresponding to the grinding parameter combinations are generated. A specific grinding parameter combination is selected based on each of the grinding simulation result combinations, and the wafer processing equipment is set accordingly.
    Type: Application
    Filed: September 12, 2023
    Publication date: May 30, 2024
    Applicant: GlobalWafers Co., Ltd.
    Inventors: Chih-Chun Cheng, Wen-Nan Cheng, Meng-Bi Lin, Chi-Feng Li, Tzu-Fan Chiang, Wei-Jen Chen, Chien Hung Chen, Hsiu Chi Liang, Ying-Ru Shih
  • Publication number: 20240178211
    Abstract: A semiconductor device is provided. The semiconductor device comprises a first semiconductor die comprising a first capacitor, and a second semiconductor die in contact with the first semiconductor die and comprises a diode. The first semiconductor die and the second semiconductor die are arranged along a first direction, and a diode is configured to direct electrons accumulated at the first capacitor to a ground.
    Type: Application
    Filed: February 5, 2024
    Publication date: May 30, 2024
    Inventors: HSIN-LI CHENG, SHU-HUI SU, YU-CHI CHANG, YINGKIT FELIX TSUI, SHIH-FEN HUANG
  • Patent number: 11996428
    Abstract: An image sensor includes an array of image pixels and black level correction (BLC) pixels. Each BLC pixel includes a BLC pixel photodetector, a BLC pixel sensing circuit, and a BLC pixel optics assembly configured to block light that impinges onto the BLC pixel photodetector. Each BLC pixel optics assembly may include a first portion of a layer stack including a vertically alternating sequence of first material layers having a first refractive index and second material layers having a second refractive index. Additionally or alternatively, each BLC pixel optics assembly may include a first portion of a layer stack including at least two metal layers, each having a respective wavelength sub-range having a greater reflectivity than another metal layer. Alternatively or additionally, each BLC pixel optics assembly may include an infrared blocking material layer that provides a higher absorption coefficient than color filter materials within image pixel optics assemblies.
    Type: Grant
    Filed: March 3, 2021
    Date of Patent: May 28, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Feng-Chien Hsieh, Yun-Wei Cheng, Kuo-Cheng Lee, Hsin-Chi Chen
  • Patent number: 11995388
    Abstract: An integrated circuit includes a first active region of a first set of transistors of a first type, a second active region of a second set of transistors of the first type, a third active region of a third set of transistors of the first type, a fourth active region of a fourth set of transistors of the first type and a fifth active region of a fifth set of transistors of a second type. The first, second, fourth and fifth active region have a first width in a second direction, and are on a first level. The third active region is on the first level, and has a second width different from the first width. The second active region is adjacent to the first boundary, and is separated from the first active region in the second direction. The fourth active region is adjacent to the second boundary.
    Type: Grant
    Filed: May 15, 2023
    Date of Patent: May 28, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Po-Sheng Wang, Chao Yuan Cheng, Chien-Chi Tien, Yangsyu Lin
  • Patent number: 11996165
    Abstract: A memory chip includes a first decoding device and a memory device. The first decoding device is configured to generate multiple word line signals. The memory device is configured to generate a third data signal based on a first data signal and a second data signal. The memory device includes a first memory circuit and a second memory circuit. The first memory circuit is configured to generate the first data signal at a first node according to the word line signals during a first period. The second memory circuit is configured to generate the second data signal at a second node different from the first node according to the word line signals during a second period after the first period. A method of operating a memory chip is also disclosed herein.
    Type: Grant
    Filed: May 17, 2022
    Date of Patent: May 28, 2024
    Assignee: AU OPTRONICS CORPORATION
    Inventors: Hsiang-Chi Cheng, Shyh-Bin Kuo, Yi-Cheng Lai, Chung-Hung Chen, Shih-Hsien Yang, Yu-Chih Wang, Kuo-Hsiang Chen
  • Publication number: 20240170536
    Abstract: A method of forming semiconductor devices having improved work function layers and semiconductor devices formed by the same are disclosed. In an embodiment, a method includes depositing a gate dielectric layer on a channel region over a semiconductor substrate; depositing a first p-type work function metal on the gate dielectric layer; performing an oxygen treatment on the first p-type work function metal; and after performing the oxygen treatment, depositing a second p-type work function metal on the first p-type work function metal.
    Type: Application
    Filed: January 29, 2024
    Publication date: May 23, 2024
    Inventors: Hsin-Yi Lee, Ji-Cheng Chen, Chi On Chui
  • Patent number: 11990557
    Abstract: There is provided an optical sensor package including a substrate, a base layer, an optical detection region, a light source and a light blocking wall. The base layer is arranged on the substrate. The light detection region and the light source are arranged on the base layer. The light blocking wall is arranged on the base layer, and located between the light detection region and the light source to block light directly propagating from the light source to the light detection region.
    Type: Grant
    Filed: October 29, 2020
    Date of Patent: May 21, 2024
    Assignee: PIXART IMAGING INC.
    Inventors: Chi-Chih Shen, Kuo-Hsiung Li, Shang-Feng Hsieh, Jui-Cheng Chuang, Yi-Chang Chang
  • Patent number: 11989066
    Abstract: In one or more embodiments, a fan circuit may be configured with an input of a first amplifier coupled to a revolution indicator associated with a fan; an output of the first amplifier coupled to an input of a second amplifier; and a power supply input of the second amplifier coupled to a first contact of a first connector. In one or more embodiments, the first contact of the first connector may be coupled to a first contact of a second connector to drive a resistive load coupled to the first contact of the second connector; a second contact of the first connector may be coupled to a second contact of the second connector to provide a reference voltage to the second amplifier; and the second amplifier may provide amplified signals to the first contact of the first connector based at least on signals received from the revolution indicator.
    Type: Grant
    Filed: January 21, 2022
    Date of Patent: May 21, 2024
    Assignee: Dell Products L.P.
    Inventors: Chi-Chang Fu, Feng Cheng Su, Chen Chi Hsieh
  • Publication number: 20240156683
    Abstract: Disclosed is a reusable actuator for use with a drug container including a stopper comprising a container having a closed end, an open end, and a sidewall extending therebetween in a longitudinal direction, an electrode disposed inside the container for use in generating a gas, an actuating element disposed at and closing the open end of the container, the actuating element and the container defining an actuator interior, wherein the actuating element is movable relative to the container in the longitudinal direction by a gas pressure of the gas in the actuator interior, such that the actuating element applies a force to the stopper to cause a drug delivery from the drug container, and a retracting mechanism for use in removing the gas to assist the actuating element's retraction for reuse.
    Type: Application
    Filed: November 16, 2023
    Publication date: May 16, 2024
    Applicant: MicroMED Co., Ltd.
    Inventors: Chia-Chi FENG, Po-Ying LI, Hong Jun YEH, Kuang-Hsiang CHENG
  • Publication number: 20240162333
    Abstract: Semiconductor devices and methods of manufacturing are presented in which inner spacers for nanostructures are manufactured. In embodiments a dielectric material is deposited for the inner spacer and then treated. The treatment may add material and cause an expansion in volume in order to close any seams that can interfere with subsequent processes.
    Type: Application
    Filed: January 24, 2024
    Publication date: May 16, 2024
    Inventors: Wan-Yi Kao, Hung Cheng Lin, Che-Hao Chang, Yung-Cheng Lu, Chi On Chui
  • Publication number: 20240164156
    Abstract: Disclosed is a display substrate including a base substrate, which includes first and second display regions, and at least one first data line. The first display region includes first and second sub-display regions located on opposite sides of the second display region along a first direction; and a third sub-display region located on at least one side of the second display region along a second direction. The first data line includes a first sub-data line located in the first sub-display region and connected with a pixel circuit of the first sub-display region, a second sub-data line located in the second sub-display region and connected with a pixel circuit of the second sub-display region, and a third sub-data line which is connected with the first and second sub-data lines, located in the third sub-display region, and connected with at least one second pixel circuit of the third sub-display region.
    Type: Application
    Filed: June 23, 2021
    Publication date: May 16, 2024
    Inventors: Jianchang CAI, Chi YU, Bo SHI, Yudiao CHENG, Zhi WANG, Benlian WANG
  • Patent number: 11982944
    Abstract: A method of lithography process is provided. The method includes forming a conductive layer over a reticle. The method includes applying ionized particles to the reticle by a discharging device. The method includes forming a photoresist layer over a semiconductor substrate. The method includes securing the semiconductor substrate by a wafer electrostatic-clamp. The method also includes patterning the photoresist layer by emitting radiation from a radiation source via the reticle.
    Type: Grant
    Filed: May 31, 2023
    Date of Patent: May 14, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Hsiao-Lun Chang, Chueh-Chi Kuo, Tsung-Yen Lee, Tzung-Chi Fu, Li-Jui Chen, Po-Chung Cheng, Che-Chang Hsu
  • Patent number: 11984649
    Abstract: A wearable device includes a conducting frame, a circuit board, and a grounding member. The conducting frame includes a first part and a second part that are separated. The circuit board has a system grounding surface and is disposed inside the conducting frame. The grounding member is disposed inside the conducting frame and connected to the first part. The first part and the grounding member are formed as a first antenna. The first part has a first feeding terminal. The grounding member has a first grounding terminal, and the first grounding terminal is connected to the system grounding surface of the circuit board. The second part is formed as a second antenna. The second antenna has a second feeding terminal, a second grounding terminal, and a third grounding terminal. The second and the third grounding terminals are connected to the system grounding surface of the circuit board.
    Type: Grant
    Filed: May 6, 2022
    Date of Patent: May 14, 2024
    Assignee: PEGATRON CORPORATION
    Inventors: Kuo-Chi Cheng, Po-Yen Lai, Ping-Hung Lu
  • Patent number: 11984314
    Abstract: A particle removal method for removing particles on the backside of a reticle is provided. The method includes disposing the reticle on a reticle holder. In addition, the method includes moving a baffle defining an enclosed area that encompasses a particle to be removed on a backside of the reticle. The method further includes spraying, by a solution spraying module of a particle removal device, a solution onto the particle. The method further includes sucking, by a sucking module of the particle removal device, the solution on the reticle with the particle. The method further includes emitting, by the particle removal device, a gas onto the backside of the reticle for drying the backside.
    Type: Grant
    Filed: July 9, 2021
    Date of Patent: May 14, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Siao-Chian Huang, Po-Chung Cheng, Ching-Juinn Huang, Tzung-Chi Fu, Tsung-Yen Lee
  • Publication number: 20240152671
    Abstract: A violation checking method includes generating a violation log report for a design, classifying violation logs in the violation log report into high-risk logs and low-risk logs by a machine learning model, reviewing the high-risk logs, and modifying the design if at least one bug is identified in the high-risk logs.
    Type: Application
    Filed: November 3, 2023
    Publication date: May 9, 2024
    Applicant: MEDIATEK INC.
    Inventors: Chi-Ming Lee, Chung-An Wang, Cheok Yan Goh, Chia-Cheng Tsai, Chien-Hsin Yeh, Chia-Shun Yeh, Chin-Tang Lai
  • Publication number: 20240154016
    Abstract: A device includes a first nanostructure; a second nanostructure over the first nanostructure; a first high-k gate dielectric disposed around the first nanostructure; a second high-k gate dielectric being disposed around the second nanostructure; and a gate electrode over the first high-k gate dielectric and the second high-k gate dielectric. A portion of the gate electrode between the first nanostructure and the second nanostructure comprises a first portion of a p-type work function metal filling an area between the first high-k gate dielectric and the second high-k gate dielectric.
    Type: Application
    Filed: January 17, 2024
    Publication date: May 9, 2024
    Inventors: Hsin-Yi Lee, Ji-Cheng Chen, Cheng-Lung Hung, Chi On Chui
  • Patent number: 11976018
    Abstract: Disclosed is a diamine compound represented by Formula (1), in which R1, R2, R3, R4, R5, X1, X2, X3, X4, m, n, a, b, c, and d are as defined herein. Also disclosed are a method for manufacturing the diamine compound, a composition including the diamine compound having a (chain alkoxy-methylene) phenyl group or a (hydroxyl-methylene) phenyl group, and a polymer including the (chain alkoxy-methylene) phenyl group or the (hydroxyl-methylene) phenyl group.
    Type: Grant
    Filed: March 9, 2021
    Date of Patent: May 7, 2024
    Assignee: DAXIN MATERIALS CORP.
    Inventors: Kai-Sheng Jeng, Yuan-Li Liao, You-Ming Chen, Yu-Ying Kuo, Shao-Chi Cheng