Abstract: The present disclosure describes a method to form a backside power rail (BPR) semiconductor device with an air gap. The method includes forming a fin structure on a first side of a substrate, forming a source/drain (S/D) region adjacent to the fin structure, forming a first S/D contact structure on the first side of the substrate and in contact with the S/D region, and forming a capping structure on the first S/D contact structure. The method further includes removing a portion of the first S/D contact structure through the capping structure to form an air gap and forming a second S/D contact structure on a second side of the substrate and in contact with the S/D region. The second side is opposite to the first side.

Abstract: A wireless communication device and an antenna matching circuit are provided. The wireless communication device includes an RF transceiver, a first SPDT switch, a low noise amplifier, a power amplifier, and the antenna matching circuit. The antenna matching circuit includes a second SPDT switch, a first antenna element, a second antenna element, a first transmission path, a second transmission path, and a plurality of SPST switches. The second SPDT switch is connected to the first SPDT switch. When the antenna matching circuit is switched to a first mode, the second SPDT switch is switched to the first transmission path, and the first antenna element is used to generate a first radiation pattern. When the antenna matching circuit is switched to a second mode, the second SPDT switch is switched to the second transmission path, and the second antenna element is used to generate a second radiation pattern.

Abstract: The present invention relates to a Cu ion sensor, which greatly improves the sensitivity to Cu by a nitrogen-rich surface of a copper nitride thin film doped with a metal material. The present invention also relates to a Cu ion sensing method, in which Cu2+ is detected by contacting the Cu ion sensor of the present invention with the solution to be tested, and using the change in electrical conductivity of a copper nitride film doped with a metal material in the presence of Cu2+ in the solution.

Abstract: Some embodiments of the present disclosure relate to a processing tool. The tool includes a housing enclosing a processing chamber, and an input/output port configured to pass a wafer through the housing into and out of the processing chamber. A back-side macro-inspection system is arranged within the processing chamber and is configured to image a back side of the wafer. A front-side macro-inspection system is arranged within the processing chamber and is configured to image a front side of the wafer according to a first image resolution. A front-side micro-inspection system is arranged within the processing chamber and is configured to image the front side of the wafer according to a second image resolution which is higher than the first image resolution.

Abstract: A semiconductor device with dual side source/drain (S/D) contact structures and a method of fabricating the same are disclosed. The method includes forming a fin structure on a substrate, forming a superlattice structure on the fin structure, forming first and second S/D regions within the superlattice structure, forming a gate structure between the first and second S/D regions, forming first and second contact structures on first surfaces of the first and second S/D regions, and forming a third contact structure, on a second surface of the first S/D region, with a work function metal (WFM) silicide layer and a dual metal liner. The second surface is opposite to the first surface of the first S/D region and the WFM silicide layer has a work function value closer to a conduction band energy than a valence band energy of a material of the first S/D region.

Abstract: A semiconductor device structure includes a source/drain feature comprising a first surface, a second surface opposing the first surface, and a sidewall connecting the first surface to the second surface. The structure also includes a dielectric layer having a continuous surface in contact with the entire second surface of the source/drain feature, a semiconductor layer having a first surface, a second surface opposing the first surface, and a sidewall connecting the first surface to the second surface, wherein the sidewall of the semiconductor layer is in contact with the sidewall of the source/drain feature. The structure also includes a gate dielectric layer in contact with the continuous surface of the dielectric layer and the second surface of the semiconductor layer, and a gate electrode layer surrounding a portion of the semiconductor layer.

Abstract: Semiconductor devices and methods of forming the same are provided. A semiconductor device according to one embodiment includes an active region including a channel region and a source/drain region adjacent the channel region, a gate structure over the channel region of the active region, a source/drain contact over the source/drain region, a dielectric feature over the gate structure and including a lower portion adjacent the gate structure and an upper portion away from the gate structure, and an air gap disposed between the gate structure and the source/drain contact. A first width of the upper portion of the dielectric feature along a first direction is greater than a second width of the lower portion of the dielectric feature along the first direction. The air gap is disposed below the upper portion of the dielectric feature.

Abstract: A semiconductor device structure, along with methods of forming such, are described. The semiconductor device structure includes a device, a first dielectric material disposed over the device, and an opening is formed in the first dielectric material. The semiconductor device structure further includes a conductive structure disposed in the opening, and the conductive structure includes a first sidewall. The semiconductor device structure further includes a surrounding structure disposed in the opening, and the surrounding structure surrounds the first sidewall of the conductive structure. The surrounding structure includes a first spacer layer and a second spacer layer adjacent the first spacer layer. The first spacer layer is separated from the second spacer layer by an air gap.

Abstract: The present disclosure describes a method that mitigates the formation of facets in source/drain silicon germanium (SiGe) epitaxial layers. The method includes forming an isolation region around a semiconductor layer and a gate structure partially over the semiconductor layer and the isolation region. Disposing first photoresist structures over the gate structure, a portion of the isolation region, and a portion of the semiconductor layer and doping, with germanium (Ge), exposed portions of the semiconductor layer and exposed portions of the isolation region to form Ge-doped regions that extend from the semiconductor layer to the isolation region. The method further includes disposing second photoresist structures over the isolation region and etching exposed Ge-doped regions in the semiconductor layer to form openings, where the openings include at least one common sidewall with the Ge-doped regions in the isolation region. Finally the method includes growing a SiGe epitaxial stack in the openings.

Abstract: A semiconductor device includes a first gate structure extending along a first lateral direction. The semiconductor device includes a first interconnect structure, disposed above the first gate structure, that extends along a second lateral direction perpendicular to the first lateral direction. The first interconnect structure includes a first portion and a second portion electrically isolated from each other by a first dielectric structure. The semiconductor device includes a second interconnect structure, disposed between the first gate structure and the first interconnect structure, that electrically couples the first gate structure to the first portion of the first interconnect structure. The second interconnect structure includes a recessed portion that is substantially aligned with the first gate structure and the dielectric structure along a vertical direction.

Abstract: A method includes forming a gate stack, which includes a first portion over a portion of a first semiconductor fin, a second portion over a portion of a second semiconductor fin, and a third portion connecting the first portion to the second portion. An anisotropic etching is performed on the third portion of the gate stack to form an opening between the first portion and the second portion. A footing portion of the third portion remains after the anisotropic etching. The method further includes performing an isotropic etching to remove a metal gate portion of the footing portion, and filling the opening with a dielectric material.

Abstract: In an embodiment, a method of forming a structure includes forming a first transistor and a second transistor over a first substrate; forming a front-side interconnect structure over the first transistor and the second transistor; etching at least a backside of the first substrate to expose the first transistor and the second transistor; forming a first backside via electrically connected to the first transistor; forming a second backside via electrically connected to the second transistor; depositing a dielectric layer over the first backside via and the second backside via; forming a first conductive line in the dielectric layer, the first conductive line being a power rail electrically connected to the first transistor through the first backside via; and forming a second conductive line in the dielectric layer, the second conductive line being a signal line electrically connected to the second transistor through the second backside via.

Abstract: A semiconductor device includes a first dielectric layer, a stack of semiconductor layers disposed over the first dielectric layer, a gate structure wrapping around each of the semiconductor layers and extending lengthwise along a direction, and a dielectric fin structure and an isolation structure disposed on opposite sides of the stack of semiconductor layers and embedded in the gate structure. The dielectric fin structure has a first width along the direction smaller than a second width of the isolation structure along the direction. The isolation structure includes a second dielectric layer extending through the gate structure and the first dielectric layer, and a third dielectric layer extending through the first dielectric layer and disposed on a bottom surface of the gate structure and a sidewall of the first dielectric layer.

Abstract: An IC structure includes a fin structure, a contact overlying the fin structure along a first direction, and an isolation layer between the contact and the fin structure. The isolation layer is adjacent to a portion of the contact along a second direction perpendicular to the first direction.

Abstract: A method of forming a semiconductor transistor device. The method comprises forming a channel structure over a substrate and forming a first source/drain structure and a second source/drain structure on opposite sides of the fin structure. The method further comprises forming a gate structure surrounding the fin structure. The method further comprises flipping and partially removing the substrate to form a back-side capping trench while leaving a lower portion of the substrate along upper sidewalls of the first source/drain structure and the second source/drain structure as a protective spacer. The method further comprises forming a back-side dielectric cap in the back-side capping trench.

Abstract: A backside metallized compound semiconductor device includes a compound semiconductor wafer and a metal layered structure. The compound semiconductor wafer includes a substrate having opposite front and back surfaces, and a ground pad structure formed on the front surface. The substrate is formed with a via extending from the back surface to the front surface to expose a side wall of the substrate and a portion of the ground pad structure. The metal layered structure is disposed on the back surface, and covers the side wall and the portion of the ground pad structure. The metal layered structure includes an adhesion layer, a seed layer, a gold layer, and an electroplated copper layer that are formed on the back surface in such order. The method for manufacturing the backside metallized compound semiconductor device is also disclosed.

Abstract: In some embodiments, the present disclosure relates to an integrated chip structure. The integrated chip structure includes a substrate. A gate electrode is over the substrate and a spacer structure laterally surrounds the gate electrode. A conductive via is disposed on the gate electrode. A liner is arranged along one or more sidewalls of the spacer structure. The conductive via has a bottommost surface that has a larger width than a part of the conductive via that is laterally adjacent to one or more interior sidewalls of the liner.

Abstract: A management method for a cutting tool of a machine tool is provided. A user host imports a graphical data of a workpiece and a cutting tool database into CAM, and a user may select cutting tools to establish a complete machining process. T codes are replaced with electronic tags. Before executing a machine code comprising the electronic tags, the machine tool re-scans the cutting tools assembled at a tool turret and updates cutting tool arrangement information to ensure that the tool turret is equipped with the cutting tools used in the machining process. When the machine tool stores the electronic tags, a ready message is displayed for reminding an operator. When the electronic tags are not stored, the current storage location of a cutting tool lacked in the machining process or a warning message is displayed at the operation interface for reminding the operator.

Abstract: A method for forming a semiconductor device structure is provided. The method includes forming a first insulating layer over a substrate. A first metal feature is formed in the first insulating layer and a second insulating layer is formed over the first insulating layer. A first metal via is formed through the second insulating layer to connect the first metal feature. A second metal feature is formed over the second insulating layer. The second metal feature has a convex top surface and a plane bottom surface, and the plane bottom is electrically connected to the first metal feature through the first metal via.

Abstract: A semiconductor device and method of manufacturing the same are provided. The semiconductor device includes a substrate and a gate structure disposed on the substrate. The semiconductor device also includes a source region and a drain region disposed within the substrate. The substrate includes a drift region laterally extending between the source region and the drain region. The semiconductor device further includes a first stressor layer disposed over the drift region of the substrate. The first stressor layer is configured to apply a first stress to the drift region of the substrate. In addition, the semiconductor device includes a second stressor layer disposed on the first stressor layer. The second stressor layer is configured to apply a second stress to the drift region of the substrate, and the first stress is opposite to the second stress.