Abstract: An optical detection device of detecting a target container includes a linear light source, an optical sensor array and a processor. The linear light source is adapted to project a long strip illumination beam onto the target container. The optical sensor array includes a plurality of sensing units arranged as a long strip adapted to receive a long strip detection beam reflected from the target container. The processor is electrically connected to the optical sensor array. The processor is adapted to analyze intensity distribution of the plurality of sensing units to acquire a relative distance between the optical sensor array and a rim of the target container.

Abstract: A high electron mobility transistor (HEMT) includes a buffer layer on a substrate, a barrier layer on the buffer layer, a gate electrode on the barrier layer, a field plate adjacent to two sides of the gate electrode, and a first passivation layer adjacent to two sides of the gate electrode. Preferably, a sidewall of the field plate includes a first curve.

Abstract: A switched capacitor voltage converter circuit for converting a first voltage to a second voltage includes: an output capacitor; a switched capacitor converter; and a control circuit. The switched capacitor converter includes: a switch circuit including fourth switches; an inductor coupled between the switch circuit and the output capacitor; and a flying capacitor coupled to the switch circuit, wherein the flying capacitor and the output capacitor constitute a voltage divider. The control circuit generates a PWM signal according to the second voltage and generates switch signals according to the PWM signal to control the switch circuit, so as to convert the first voltage to the second voltage. The control circuit decides whether the switched capacitor converter operates in a boundary conduction mode, a discontinuous conduction mode or a continuous conduction mode according to an output current or an output current related signal.

Abstract: There is provided an optical sensor including a pixel matrix and a readout circuit. The pixel matrix includes multiple pixels arranged in a matrix, and each of the multiple pixels outputs temporal difference pixel data. The readout circuit sequentially reads the pixel matrix using a readout block, and performs the hybrid difference calculation on the temporal difference pixel data of pixels within the readout block. Accordingly, the output of the readout circuit is the data accomplishing temporal difference and spatial difference.

Abstract: The present disclosure is directed to a transfer blade including a first end segment, a second end segment opposite to the first end segment, and an intermediate segment extending from the first end segment to the second end segment. The first end segment includes a first contact region and the second end segment includes a second contact region. The first and second contact regions are configured to contact locations of a surface of a workpiece that do not overlap or are not aligned with a sensitive area of the workpiece. The sensitive area of the workpiece may be an EUV frame or a reticle of the workpiece. A non-contact region extends continuously along the first end segment, the intermediate segment, and the second end segment, and the non-contact region overlaps the sensitive area of the workpiece and is spaced apart from the sensitive area of the workpiece.

Abstract: Non-planar I/O and logic semiconductor devices having different workfunctions on common substrates and methods of fabricating non-planar I/O and logic semiconductor devices having different workfunctions on common substrates are described. For example, a semiconductor structure includes a first semiconductor device disposed above a substrate. The first semiconductor device has a conductivity type and includes a gate electrode having a first workfunction. The semiconductor structure also includes a second semiconductor device disposed above the substrate. The second semiconductor device has the conductivity type and includes a gate electrode having a second, different, workfunction.

Abstract: A switched capacitor voltage converter circuit includes: a switched capacitor converter and a control circuit. The switched capacitor converter includes at least one resonant capacitor, switches and at least one inductor. The control circuit generates a pulse width modulation (PWM) signal according to a first voltage or a second voltage and generates a control signal according to the PWM signal and a zero current detection signal. The control signal controls the switched capacitor converter by operating the corresponding switches to switch electrical connection of the inductor, so as to convert the first voltage to the second voltage or convert the second voltage to the first voltage.

Abstract: A semiconductor device includes a substrate having a magnetic tunneling junction (MTJ) region and a logic region, an inter-metal dielectric (IMD) layer on the substrate, a MTJ in the IMD layer on the MTJ region, a first metal interconnection in the IMD layer on the logic region, and protrusions adjacent to two sides of the first metal interconnection. Preferably, the MTJ further includes a bottom electrode, a fixed layer, a barrier layer, a free layer, and a top electrode.

Abstract: A semiconductor package structure includes a semiconductor device with an active surface, a conductive pillar on the conductive pad, an adhesion strengthening layer, and an encapsulant in contact with the adhesion strengthening layer. The conductive pillar has a side surface and a top surface. The adhesion strengthening layer is conformally disposed on the side surface of the conductive pillar and the active surface of the semiconductor device.

Abstract: A system based upon artificial neural networks generates attenuation-corrected SPECT from non-attenuation-corrected SPECT (single photon emission computed tomography) without or with an intermediate step of attenuation map estimation. The system includes a SPECT scanner with CZT cameras for dynamic SPECT imaging. The system also includes a machine learning system including a 3D Dual Squeeze-and-Excitation Residual Dense Network for generating attenuation-corrected SPECT or attenuation maps from non-attenuation-corrected SPECT. The machine learning system reconstructs images from photopeak window and one or more scatter windows of the SPECT scanner are fed to the 3D Dual Squeeze-and-Excitation Residual Dense Network to generate attenuation-corrected SPECT or attenuation maps.

Abstract: A semiconductor package structure and a method of manufacturing the same are provided. The semiconductor package structure includes a first electronic component, a second electronic component, and a reinforcement component. The reinforcement component is disposed above the first electronic component and the second electronic component. The reinforcement component is configured to reduce warpage.

Abstract: A power converter includes first to fourth switches, a flying capacitor, an inductor, an output capacitor and a control circuit. The first to fourth switches are sequentially coupled in cascode. The first switch receives an input voltage, and the fourth switch is further coupled to a ground terminal. The flying capacitor is coupled across the second switch and the third switch, the inductor is coupled to the second switch, the third switch and the output capacitor. The output capacitor is used to output an output voltage. In a non-regulated mode, the control circuit switches the first to fourth switches according to a resonant frequency. In a regulated mode, the control circuit switches the first to fourth switches according to a regulated frequency exceeding the resonant frequency. When the flying capacitor is coupled to the inductor, the flying capacitor and the inductor can form a resonant circuit having the resonant frequency.

Abstract: A power converter includes first to fourth switches, a flying capacitor, an inductor, an output capacitor and a control circuit. The first to fourth switches are sequentially coupled in cascode. The first switch is used to receive an input voltage. The flying capacitor is coupled across the second switch and the third switch, the inductor is coupled to the second switch, the third switch and the output capacitor. The output capacitor is used to output an output voltage. When the input voltage is less than an input voltage threshold, the control circuit is used to switch the first to fourth switches according to a resonant frequency. When the input voltage exceeds the input voltage threshold, the control circuit switch is used to the first to fourth switches according to a regulated frequency exceeding the resonant frequency.

Abstract: There is provided a pixel circuit for performing analog operation including a photodiode, a first temporal circuit, a second temporal circuit and an operation circuit. Within a first interval, the photodiode detects first light energy to be stored in the first temporal circuit. Within a second interval, the photodiode detects second light energy to be stored in the second temporal circuit. Within an operation interval, the first temporal circuit outputs a first detection signal having a first pulse width according to the first light energy and outputs a second detection signal having a second pulse width according to the second light energy for being calculated by the operation circuit.

Abstract: A high electron mobility transistor (HEMT) includes a buffer layer on a substrate, a barrier layer on the buffer layer, a gate electrode on the barrier layer, a field plate adjacent to two sides of the gate electrode, and a first passivation layer adjacent to two sides of the gate electrode. Preferably, a sidewall of the field plate includes a first curve.

Abstract: There is provided an optical sensor including a pixel matrix and a readout circuit. The pixel matrix includes multiple pixels arranged in a matrix, and each of the multiple pixels outputs temporal difference pixel data. The readout circuit sequentially reads the pixel matrix using a readout block, and performs the hybrid difference calculation on the temporal difference pixel data of pixels within the readout block. Accordingly, the output of the readout circuit is the data accomplishing temporal difference and spatial difference.

Abstract: Arousal events can be determined for a user associated with a wearable device, such as a user wearing a wearable computing device including one or more sensors. The one or more sensors may obtain EDA information that may determine a sympathetic nervous system response of the user, which may be responsive to an arousal event or an activation. Detection of events that increase the EDA response may provide information to the user regarding arousal events and provide recommendations to the user to address the arousal events to decrease their response.

Abstract: A memory device includes a first electrode, a first support layer, a dielectric layer and a second electrode. The first electrode is disposed on a substrate and extending upwards. The first support layer laterally supports an upper portion of a sidewall of the first electrode, where the first support layer has a slim portion. The dielectric layer is disposed on the first electrode and the first support layer. The second electrode is disposed on the dielectric layer. In addition, a method of fabricating the memory device is provided.

Abstract: A semiconductor device includes a substrate having a magnetic tunneling junction (MTJ) region and a logic region, an inter-metal dielectric (IMD) layer on the substrate, a MTJ in the IMD layer on the MTJ region, a first metal interconnection in the IMD layer on the logic region, and protrusions adjacent to two sides of the first metal interconnection. Preferably, the MTJ further includes a bottom electrode, a fixed layer, a barrier layer, a free layer, and a top electrode.

Abstract: There is provided a logic circuit capable of preventing latch-up. The conducting of a parasitic SCR is prevented by doping an additional N+ active region in the N well region of a PMOS transistor and doping an additional P+ active region in the P well region of an NMOS transistor so as to prevent the occurrence of latch-up.