Abstract: In one or more embodiments, an information handling system may include multiple fans, a chassis configured to house components of the information handling system, and at least one mat fastened to the chassis, among others. For example, the chassis may include multiple holes through the chassis. For instance, the at least one mat may cover the multiple holes. In one or more embodiments, the at least one mat and the multiple holes may be configured to reduce acoustic energy within the chassis produced by the multiple fans.

Abstract: The present disclosure provides a structure and method of fabricating the structure. The structure comprises a cavity enclosed by a first substrate and a second substrate opposite to the first substrate. Further, the structure includes a feature in the cavity and the feature is protruded from a surface of the first substrate. In addition, the structure includes a dielectric layer over the feature, wherein the dielectric layer includes a first surface in contact with the feature and a second surface opposite to the first surface is positioned toward the cavity.

Abstract: A backlight module is provided. The backlight module includes a substrate having a substrate surface, a conductive layer disposed on the substrate surface, a plurality of LED chips disposed on and electrically connected to the conductive layer, a light-permeable layer having a light-permeable surface away from the substrate surface, and a pattern layer disposed on the light-permeable surface and having a plurality of first patterns corresponding to and respectively located above the plurality of LED chips. Wherein, each first pattern has a maximum width. A maximum width of one first pattern satisfies the following formula: WP?2n(TE?TL)(1?1/n2)1/2+WL; wherein WP is the maximum width of one first pattern, n is a refractivity of the light-permeable layer, TE is a thickness of the light-permeable layer, TL is a thickness of the LED chip, WL is a maximum width of LED chip corresponding to the first pattern.

Abstract: The present invention relates to an optical stack and an organic light emitting diode display including the optical stack, wherein the optical stack has an adhesive layer. The adhesive layer is disposed between a cover plate and a circular polarizer component, between the circular polarizer component and a touch component, or between the touch component and a display component. Wherein, a storage modulus at 60° C. of the adhesive layer is between 15 kPa and 30 kPa, and a ratio of a storage modulus at ?30° C. to the storage modulus at 60° C. of the adhesive layer is between 6 and 16.

Abstract: The invention discloses a control method in use of a synchronous rectifier controller, controlling a synchronous rectifier in a power supply supplying power a load. The synchronous rectifier is turned ON in response to a terminal signal of the synchronous rectifier. An ON-time of the synchronous rectifier is made not less than a minimum ON-time. A detection result in association with the load is provided, for determining the minimum ON-time. The minimum ON-time is a first period when the detection result indicates the load as a first load, and a second period, shorter than the first period, when the detection result indicates the load as a second load heavier than the first load.

Abstract: Optical modules and methods of forming the same are provided. In an embodiment, an exemplary method includes forming multiple first optical elements over a first wafer, forming multiple second optical elements over a second wafer, forming multiple third optical elements over a third wafer, aligning the first wafer with the second wafer such that, upon the aligning of the first wafer with the second wafer, each first optical element is vertically overlapped with a corresponding second optical element. The method also includes bonding the first wafer with the second wafer to form a first bonded structure, aligning the second wafer with the third wafer such that, and upon bonding the second wafer of the first bonded structure to the third wafer, where upon the aligning of the second wafer with the third wafer, each second optical element is vertically overlapped with a corresponding third optical element.

Abstract: The present disclosure provides a structure. The structure comprises a cavity enclosed by a first substrate and a second substrate opposite to the first substrate. Further, the structure includes a feature in the cavity and the feature is protruded from a surface of the first substrate. In addition, the structure includes a dielectric layer over the feature, wherein the dielectric layer includes a first surface in contact with the feature and a second surface opposite to the first surface is positioned toward the cavity.

Abstract: A secondary controller applied to a secondary side of a power converter includes a control signal generation circuit and a gate control signal generation circuit. The gate control signal generation circuit generates a gate control signal, and generates an injection signal according to the gate control signal. When a superposition voltage is less than a reference voltage, the control signal generation circuit generates a gate pulse control signal, wherein the gate pulse control signal corresponds to an output voltage of the power converter and the injection signal, the gate control signal generation circuit is further used for generating a gate pulse signal according to the gate pulse control signal, and the gate pulse signal is used for making a primary side of the power converter turned on.

Abstract: A backlight module is provided. The backlight module includes a substrate having a substrate surface, a conductive layer disposed on the substrate surface, a plurality of LED chips disposed on and electrically connected to the conductive layer, a light-permeable layer having a light-permeable surface away from the substrate surface, and a pattern layer disposed on the light-permeable surface and having a plurality of first patterns corresponding to and respectively located above the plurality of LED chips. Wherein, each first pattern has a maximum width. A maximum width of one first pattern satisfies the following formula: WP?2n(TE?TL)(1?1/n2)1/2+WL; wherein WP is the maximum width of one first pattern, n is a refractivity of the light-permeable layer, TE is a thickness of the light-permeable layer, TL is a thickness of the LED chip, WL is a maximum width of LED chip corresponding to the first pattern.

Abstract: The present invention provides an output buffer including a first transistor, a second transistor and a pad-tracking circuit is disclosed. The first transistor is coupled between a supply voltage and an output node, wherein the output node is coupled to a pad. The second transistor is coupled between the output node and a reference voltage. The pad-tracking circuit is coupled to the control circuit and the first transistor, and is configured to generate a gate control signal to a gate electrode of the first transistor. The output buffer is selectively operated in an input mode and a fail-safe mode, and when the output buffer switches between the input mode and the fail-safe mode and the supply voltage of the first transistor ramps up or ramps down, the pad-tracking circuit generates the gate control signal to the gate electrode of the first transistor according to the voltage of the pad.

Abstract: A touch panel is provided in the present disclosure, including: a substrate, a conductive trace structure, and a light-shielding structure. The substrate includes a visible area and a peripheral area, and the visible area is surrounded by the peripheral area. A conductive trace structure is disposed on the visible area. The light-shielding structure includes a first material layer and a second material layer, in which the optical density of the light-shielding structure is lower than 4, the first material layer is disposed on the peripheral area, and the second material layer is disposed on the first material layer. A method of manufacturing a touch panel is provided in some embodiments of the present disclosure for the effects of saving cost and improving wire drift.

Abstract: A method for segmenting a neural network, implemented in an electronic device, includes assigning a plurality of operator groups to a plurality of execution units based on a plurality of segmentation methods; determining operation times of the plurality of execution units and discrete degree of the operation times of the plurality of execution units in each of the plurality of segmentation methods; and segmenting the neural network according to the segmentation method with a lowest discrete degree.

Abstract: An image detection method obtains a neural network model including n operators. End operators are determined from the n operators. An image is input into the neural network model. Whether to delete operation results of the n operators is determined according to the n operators and the end operators when the neural network model processes the image using the n operators. A detection result of the image is output according to the operation results. The method can improve an efficiency of image detection.

Abstract: An image detection and classification method for faster detection and classification by a neural network is applied to a neural network model including n operators. The neural network model is mapped to a singly-linked list. A vector of data pairs corresponding to the singly-linked list is established, and operator subsets of the neural network model are determined according to the vector. A target image is input to the neural network model, and input data and output data of the operator subset are recorded. The neural network model is applied to detect the target image, and a detection result is output according to the input data and the output data. The method can detect images quickly.

Abstract: A method, an apparatus, and a storage medium for dividing a neural network into regions for preventing data duplication and data loss in parallel movements of data between nodes. The method includes obtaining a neural network model comprising n operators; scanning all operator groups in the neural network model; dividing the neural network model into m regions; rescanning all operator groups in the neural network model and identifying broken operator group(s); analyzing input and output of each of the n number of operators in the broken operator group(s) and identifies operators of a specific sort; and adjusting the operators of the specific type to rearranged to keep individual inputs and outputs within a single region.

Abstract: An operation power source for an operation power source supplying power to a synchronous rectifier controller is charged according to the invention. The synchronous rectifier controller controls a synchronous rectifier in response to a channel signal of the synchronous rectifier, generating SR ON times and SR OFF times. It is determined whether the channel signal resonates in a first SR OFF time, to provide an oscillation record accordingly. In a second SR OFF time after the first SR OFF time, in response to the oscillation record, a portion of resonance energy that causes the channel signal resonating is directed to charge the operation power source.

Abstract: A power supply has a transformer, a rectifier switch, a secondary-side controller and two diodes. The transformer includes a primary winding, a secondary winding, and a detection winding, inductively coupling to one another. The rectifier switch is connected in series with the secondary winding between two output power lines. The secondary-side controller is electrically coupled to two ends of the detection winding, for controlling the rectifier switch in response to two terminal signals at the two ends respectively. The two diodes are back-to-back electrically connected in series between the two ends, and a joint connecting the two diodes is electrically connected to one of the two output power lines.

Abstract: A method for manufacturing a MEMS structure is provided. The method includes providing a MEMS substrate having a first surface, forming a first buffer layer on the first surface of the MEMS substrate, and forming a first roughening layer on the first buffer layer. Also, a MEMS structure is provided. The MEMS structure includes a MEMS substrate, a first buffer layer, a first roughening layer, and a CMOS substrate. The MEMS substrate has a first surface and a pillar is on the first surface. The first buffer layer is on the first surface. The first roughening layer is on the first buffer layer. The CMOS substrate has a second surface and is bonded to the MEMS substrate via the pillar. Moreover, an air gap is between the first roughening layer and the second surface of the CMOS substrate.

Abstract: A liquid treatment apparatus includes a water pump and a plasma jet generating device. A liquid inlet of the water pump is immersed in a liquid. A liquid outlet of the water pump is configured to eject the liquid from the liquid inlet out of the water pump without artificial bubbles in the liquid. A gas inlet of the plasma jet generating device is configured to be located out of the liquid. A pair of electrodes of the plasma jet generating device is configured to generate plasma jet by the gas from the gas inlet. The plasma jet outlet is configured to be immersed in the liquid and in proximity to the liquid outlet of the water pump so that the gas is automatically entrained into the gas inlet of the plasma jet generating device when the liquid is ejected out from the liquid outlet.

Abstract: A method of processing and storing general data by means of hardware obtains initial unhashed data and a fixed value. If a value of the initial unhashed data is greater than the fixed value, the initial data is divided into N sub-data or segments. A size of each sub-data is not more than the fixed value, N being an integer greater than 1. The collection of sub sets of data is input into a memory of the electronic device after hashing.