Patents by Inventor An Chih CHU

An Chih CHU has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11180365
    Abstract: A microelectromechanical system (MEMS) device may include a MEMS structure over a first substrate. The MEMS structure comprises a movable element. Depositing a first conductive material over the first substrate and etching trenches in a second substrate. Filling the trenches with a second conductive material and depositing a third conductive material over the second conductive material and the second substrate. Bonding the first substrate and the second substrate and thinning a backside of the second substrate which exposes the second conductive material in the trenches.
    Type: Grant
    Filed: October 28, 2019
    Date of Patent: November 23, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Kai-Chih Liang, Chia-Hua Chu, Te-Hao Lee, Jiou-Kang Lee, Chung-Hsien Lin
  • Patent number: 11175354
    Abstract: A method for scanning artificial structure, wherein a scanning artificial structure apparatus comprises four magnetic-field sensors, the four magnetic-field sensors are non-coplanar configured, the method comprises following steps of: moving the scanning artificial structure apparatus along a scanning path within a to-be-tested area, in the meantime, measuring magnetic field by the four magnetic-field sensors, and recording a position sequence when measuring magnetic field, wherein four magnetic-field measurement sequences are measured by the four magnetic-field sensors; and calculating a magnetic-field variation distribution from the four magnetic-field measurement sequences and the position sequence, wherein the magnetic-field variation distribution is corresponding to at least one artificial structure distribution.
    Type: Grant
    Filed: October 4, 2019
    Date of Patent: November 16, 2021
    Assignee: NATIONAL CENTRAL UNIVERSITY
    Inventors: Chien-Chih Chen, Yi-Chen Chu, Yung-Chieh Chuang
  • Patent number: 11177154
    Abstract: A carrier structure suitable for transferring or supporting a plurality of micro devices including a carrier and a plurality of transfer units is provided. The transfer units are disposed on the carrier. Each of the transfer units includes a plurality of transfer parts. Each of the transfer parts has a transfer surface. Each of the micro devices has a device surface. The transfer surfaces of the transfer parts of each of the transfer units are connected to the device surface of corresponding micro device. The area of each of the transfer surfaces is smaller than the area of the device surface of the corresponding micro device. A micro device structure using the carrier structure is also provided.
    Type: Grant
    Filed: December 19, 2018
    Date of Patent: November 16, 2021
    Assignee: PixeLED Display CO., LTD.
    Inventors: Pei-Hsin Chen, Yi-Chun Shih, Yi-Ching Chen, Ying-Tsang Liu, Yu-Chu Li, Huan-Pu Chang, Chih-Ling Wu, Yu-Yun Lo, Tzu-Yang Lin, Yu-Hung Lai
  • Patent number: 11164814
    Abstract: A package structure includes a semiconductor die and a first redistribution circuit structure. The first redistribution circuit structure is disposed on and electrically connected to the semiconductor die, and includes a first build-up layer. The first build-up layer includes a first metallization layer and a first dielectric layer laterally wrapping the first metallization layer, wherein at least a portion of the first metallization layer is protruded out of the first dielectric layer.
    Type: Grant
    Filed: March 14, 2019
    Date of Patent: November 2, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yung-Chi Chu, Hung-Jui Kuo, Yu-Hsiang Hu, Wei-Chih Chen
  • Patent number: 11164839
    Abstract: A package structure includes a semiconductor die and a redistribution circuit structure. The redistribution circuit structure is disposed on and electrically connected to the semiconductor die and includes a patterned conductive layer, a dielectric layer, and an inter-layer film. The dielectric layer is disposed on the patterned conductive layer. The inter-layer film is sandwiched between the dielectric layer and the patterned conductive layer, and the patterned conductive layer is separated from the dielectric layer through the inter-layer film.
    Type: Grant
    Filed: May 15, 2019
    Date of Patent: November 2, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Wei-Chih Chen, Hung-Jui Kuo, Yu-Hsiang Hu, Sih-Hao Liao, Po-Han Wang, Yung-Chi Chu, Hung-Chun Cho
  • Publication number: 20210335720
    Abstract: The present disclosure describes a method for forming capping layers configured to prevent the migration of out-diffused cobalt atoms into upper metallization layers In some embodiments, the method includes depositing a cobalt diffusion barrier layer on a liner-free conductive structure that includes ruthenium, where depositing the cobalt diffusion barrier layer includes forming the cobalt diffusion barrier layer self-aligned to the liner-free conductive structure. The method also includes depositing, on the cobalt diffusion barrier layer, a stack with an etch stop layer and dielectric layer, and forming an opening in the stack to expose the cobalt diffusion barrier layer. Finally, the method includes forming a conductive structure on the cobalt diffusion barrier layer.
    Type: Application
    Filed: January 5, 2021
    Publication date: October 28, 2021
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Shuen-Shin LIANG, Chun-I TSAI, Chih-Wei CHANG, Chun-Hsien HUANG, Hung-Yi HUANG, Keng-Chu LIN, Ken-Yu CHANG, Sung-Li WANG, Chia-Hung CHU, Hsu-Kai CHANG
  • Patent number: 11158659
    Abstract: A semiconductor device structure and method for forming the same are provided. The semiconductor device structure includes an interconnect structure formed over a substrate and a passivation layer formed over the interconnect structure. The semiconductor device structure also includes an anti-acid layer formed in the passivation layer and a bonding layer formed on the anti-acid layer and the passivation layer. The anti-acid layer has a thickness that is greater than about 140 nm.
    Type: Grant
    Filed: July 30, 2018
    Date of Patent: October 26, 2021
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Yin-Shuo Chu, Chi-Chung Yu, Li-Yen Fang, Tain-Shang Chang, Yao-Hsiang Liang, Min-Chih Tsai
  • Publication number: 20210327945
    Abstract: A device is disclosed. The device includes a plurality of pixels disposed over a first surface of a semiconductor layer. The device includes a device layer disposed over the first surface. The device includes metallization layers disposed over the device layer. One of the metallization layers, closer to the first surface than any of other ones of the metallization layers, includes at least one conductive structure. The device includes an oxide layer disposed over a second surface of the semiconductor layer, the second surface being opposite to the first surface, the oxide layer also lining a recess that extends through the semiconductor layer. The device includes a spacer layer disposed between inner sidewalls of the recess and the oxide layer. The device includes a pad structure extending through the oxide layer and the device layer to be in physical contact with the at least one conductive structure.
    Type: Application
    Filed: April 17, 2020
    Publication date: October 21, 2021
    Applicant: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Keng-Ying Liao, Huai-jen Tung, Chih Wei Sung, Po-zen Chen, Yu-chien Ku, Yu-Chu Lin, Chi-Chung Jen, Yen-Jou Wu, S.S. Wang
  • Publication number: 20210327951
    Abstract: A method includes forming a dielectric layer over a first surface of a semiconductor layer, the dielectric layer including a metallization layer. The method includes forming an opening to expose a portion of the dielectric layer. The method includes forming a buffer oxide layer lining the opening. The method includes forming, according to a patternable layer, a recess in the buffer oxide layer partially extending from a second surface of the buffer oxide layer. The method includes removing the patternable layer. The method includes extending the recess through the buffer oxide layer and a portion of the dielectric layer to expose a portion of the metallization layer. The method includes filling the recess with a conductive material to form a pad structure configured to provide electrical connection to the metallization layer.
    Type: Application
    Filed: April 17, 2020
    Publication date: October 21, 2021
    Applicant: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Keng-Ying Liao, Huai-Jen Tung, Chih Wei Sung, Po-Zen Chen, Yu-Chien Ku, Yu-Chu Lin, Chi-Chung Jen, Yen-Jou Wu, Tsun-Kai Tsao, Y.L. Yang
  • Patent number: 11143675
    Abstract: An insulator applied in a probe base including a probe mounting hole, the insulator is a sheet structure having plural through holes, and the probe mounting hole is formed at the center of the insulator, and the probe mounting hole and the through hole penetrate from a first surface to a second surface of the insulator, and the regions of the first and second surfaces without the probe mounting hole and the through hole are coplanar. The probe base has a base body and at least a composite assembly, and the base body has at least a testing zone, and the composite assembly is installed in the testing zone and has at least a probe hole for installing a probe, and the insulator is installed into the probe hole.
    Type: Grant
    Filed: April 11, 2019
    Date of Patent: October 12, 2021
    Assignee: C.C.P. CONTACT PROBES CO., LTD.
    Inventors: Chien-Yu Hsieh, Yen-Chun Chen, Chih-Hui Hou, Wei-Chu Chen, Yen-Hui Lu, Ting-Chen Pan, Yen-Wei Lin, Bor-Chen Tsai
  • Publication number: 20210298140
    Abstract: In one example in accordance with the present disclosure, a computing device is described. The computing device includes a housing and a light source to illuminate through a window in the housing. The computing device also includes a controller. The controller determines a usage level of a processor of the computing device. The controller also adjusts a characteristic of the light source based on a determined usage level of the processor.
    Type: Application
    Filed: November 29, 2018
    Publication date: September 23, 2021
    Applicant: Hewlett-Packard Development Company, L.P.
    Inventors: Po-Hsien Lin, An Chih Chu
  • Publication number: 20210273069
    Abstract: A transistor device with a recessed gate structure is provided. In some embodiments, the transistor device comprises a semiconductor substrate comprising a device region surrounded by an isolation structure and a pair of source/drain regions disposed in the device region and laterally spaced apart one from another in a first direction. A gate structure overlies the device region and the isolation structure and arranged between the pair of source/drain regions. The gate structure comprises a pair of recess regions disposed on opposite sides of the device region in a second direction perpendicular to the first direction. A channel region is disposed in the device region underneath the gate structure. The channel region has a channel width extending in the second direction from one of the recess regions to the other one of the recess regions.
    Type: Application
    Filed: July 15, 2020
    Publication date: September 2, 2021
    Inventors: Chen-Liang Chu, Chien-Chih Chou, Chih-Chang Cheng, Yi-Huan Chen, Kong-Beng Thei, Ming-Ta Lei, Ruey-Hsin Liu, Ta-Yuan Kung
  • Publication number: 20210189561
    Abstract: A thin film deposition system deposits a thin film on a substrate in a thin film deposition chamber. The thin film deposition system deposits the thin film by flowing a fluid into the thin film deposition chamber. The thin film deposition system includes a byproducts sensor that senses byproducts of the fluid in an exhaust fluid. The thin film deposition system adjusts the flow rate of the fluid based on the byproducts.
    Type: Application
    Filed: November 24, 2020
    Publication date: June 24, 2021
    Inventors: Wen-Hao CHENG, Yi-Ming DAI, Yen-Yu CHEN, Hsuan-Chih CHU
  • Publication number: 20210152000
    Abstract: A support base includes a casing, a signal transmission module, a connection port, an audio output element and a detecting module. The support base is connected with a portable electronic device through the signal transmission module. The support base is connected with an external electronic device through the connection port. A first audio signal from the portable electronic device or a second audio signal from the external electronic device can be played by the audio output element. The detecting module detects the connection status of the support base. According to the connection status, the first audio signal or the second audio signal is controlled to be outputted from the audio output element.
    Type: Application
    Filed: August 27, 2020
    Publication date: May 20, 2021
    Inventors: Wen-Chih Chu, Yi-Ting Chang, Yu-Chuan Liu, Wen-Hsien Chan, Yu-Cun Chu
  • Publication number: 20210118700
    Abstract: The present disclosure provides a flexible workpiece pedestal capable of tilting a workpiece support surface. The workpiece pedestal further includes a heater mounted on the workpiece support surface. The heater includes a plurality of heating sources such as heating coils. The plurality of heating sources in the heater allows heating the workpiece at different temperatures for different zones of the workpiece. For example, the workpiece can have a central zone heated by a first heating coil, a first outer ring zone that is outside of the central zone heated by a second heating coil, a second outer ring zone that is outside of the first outer ring zone heated by a third heating coil. By using the tunable heating feature and the tilting feature of the workpiece pedestal, the present disclosure can reduce or eliminate the shadowing effect problem of the related workpiece pedestal in the art.
    Type: Application
    Filed: October 18, 2019
    Publication date: April 22, 2021
    Inventors: Hsuan-Chih Chu, Wen-Hao Cheng, Yen-Yu Chen, Yi-Ming Dai
  • Publication number: 20210071295
    Abstract: Sputtering systems and methods are provided. In an embodiment, a sputtering system includes a chamber configured to receive a substrate, a sputtering target positioned within the chamber, and an electromagnet array over the sputtering target. The electromagnet array includes a plurality of electromagnets.
    Type: Application
    Filed: November 23, 2020
    Publication date: March 11, 2021
    Inventors: Hsuan-Chih Chu, Chien-Hsun Pan, Yen-Yu Chen, Chun-Chih Lin
  • Publication number: 20210025882
    Abstract: The present invention relates to an equipment for enabling and accelerating uniform reaction between a to-be-reacted substance contained in a porous substrate and a reactant, and the equipment comprises: a machine body having a draining bottom plate on which the porous substrate can be placed; and a coating head which is provided above the machine body, can be moved horizontally along the porous substrate while maintaining a predetermined height, and has one or more slits, wherein each slit has an injection opening at one end and a liquid output opening at the other end.
    Type: Application
    Filed: August 14, 2020
    Publication date: January 28, 2021
    Inventors: An-Bang WANG, Chia-Chih CHU, Shih-Yi CHAO, Hung-Nien CHIU, Chun-An CHEN, Shih-Chung CHANG, Jen-Ren WANG
  • Patent number: 10859908
    Abstract: A method for fabricating a pellicle assembly for a lithography process includes providing a carrier. A membrane layer is fabricated over the carrier. A pellicle frame is attached to the membrane layer. The carrier is then separated from the membrane layer using a release treatment process.
    Type: Grant
    Filed: December 1, 2017
    Date of Patent: December 8, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chun-Hao Tseng, Sheng-Chi Chin, Yuan-Chih Chu
  • Patent number: 10844477
    Abstract: Sputtering systems and methods are provided. In an embodiment, a sputtering system includes a chamber configured to receive a substrate, a sputtering target positioned within the chamber, and an electromagnet array over the sputtering target. The electromagnet array includes a plurality of electromagnets.
    Type: Grant
    Filed: November 8, 2017
    Date of Patent: November 24, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Hsuan-Chih Chu, Chien-Hsun Pan, Yen-Yu Chen, Chun-Chih Lin
  • Patent number: 10816891
    Abstract: A method of manufacturing a mask includes depositing an end-point layer over a light transmitting substrate, depositing a phase shifter over the end-point layer, depositing a hard mask layer over the phase shifter, and removing a portion of the hard mask layer and a first portion of the phase shifter to expose a portion of the end-point layer. The end-point layer and the light transmitting substrate are transparent to a predetermined wavelength.
    Type: Grant
    Filed: April 6, 2017
    Date of Patent: October 27, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Hao-Ming Chang, Chien-Hung Lai, Cheng-Ming Lin, Hsuan-Wen Wang, Min-An Yang, S. C. Hsu, Shao-Chi Wei, Yuan-Chih Chu