Patents by Inventor An-Chih Wang

An-Chih Wang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240195082
    Abstract: An antenna structure includes a ground element, a feeding radiation element, a first radiation element, a second radiation element, a shorting radiation element, a third radiation element, and a fourth radiation element. The feeding radiation element has a feeding point. The first radiation element is coupled to the feeding radiation element. The second radiation element is coupled to the feeding radiation element. The second radiation element and the first radiation element substantially extend in opposite directions. The feeding radiation element is further coupled through the shorting radiation element to the ground element. The third radiation element is coupled to the ground element. The third radiation element is adjacent to the first radiation element. The fourth radiation element is coupled to the ground element. The fourth radiation element is adjacent to the second radiation element.
    Type: Application
    Filed: January 12, 2023
    Publication date: June 13, 2024
    Inventors: Yi-Chih LO, Chung-Ting HUNG, Chun-Yuan WANG, Chun-I CHEN, Jing-Yao XU, Yan-Cheng HUANG, Chu-Yu TANG
  • Publication number: 20240192426
    Abstract: A backlight module is provided and includes a circuit board, a light emitting component disposed on the circuit board, a light guiding component, a first light reflecting component and a second light reflecting component. The first light reflecting component covers at least a portion of a first surface of the light guiding component adjacent to the circuit board. The second light reflecting component includes a first light reflecting portion and a second light reflecting portion. The first light reflecting portion extends along a first direction and covers at least a portion of a second surface of the light guiding component away from the circuit board. The second light reflecting portion is connected to the first light reflecting portion and extends along a second direction. The second reflecting portion is located corresponding to a third surface of the light guiding component. Besides, a related light emitting electronic device is provided.
    Type: Application
    Filed: April 12, 2023
    Publication date: June 13, 2024
    Applicant: Wistron Corporation
    Inventors: Bin Luo, RuiHua Wang, Chih-Chou Chou
  • Publication number: 20240186123
    Abstract: Embodiments of substrate supports for process chambers are provided herein. In some embodiments, a substrate support for a process chamber includes: a pedestal having a support surface for supporting a substrate, one or more heating elements disposed therein, and a radio frequency (RF) electrode disposed therein; a hollow shaft coupled to a lower surface of the pedestal; and an RF rod extending through the hollow shaft and coupled to the RF electrode, wherein an impedance of the RF rod is less than about 0.2 ohms.
    Type: Application
    Filed: December 2, 2022
    Publication date: June 6, 2024
    Inventors: Yao-Hung YANG, Chih-Yang CHANG, Yikai CHEN, Rongping WANG
  • Patent number: 12004431
    Abstract: A semiconductor device includes a bottom electrode; a magnetic tunneling junction (MTJ) element over the bottom electrode; a top electrode over the MTJ element; and a sidewall spacer abutting the MTJ element, wherein at least one of the bottom electrode, the top electrode, and the sidewall spacer includes a magnetic material.
    Type: Grant
    Filed: March 19, 2021
    Date of Patent: June 4, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Tsung-Chieh Hsiao, Po-Sheng Lu, Wei-Chih Wen, Liang-Wei Wang, Yu-Jen Wang, Dian-Hau Chen, Yen-Ming Chen
  • Patent number: 11997842
    Abstract: A fan-out package includes a redistribution structure having redistribution-side bonding structures, a plurality of semiconductor dies including a respective set of die-side bonding structures that is attached to a respective subset of the redistribution-side bonding structures through a respective set of solder material portions, and an underfill material portion laterally surrounding the redistribution-side bonding structures and the die-side bonding structures of the plurality of semiconductor dies. A subset of the redistribution-side bonding structures is not bonded to any of the die-side bonding structures of the plurality of semiconductor dies and is laterally surrounded by the underfill material portion, and is used to provide uniform distribution of the underfill material during formation of the underfill material portion.
    Type: Grant
    Filed: August 31, 2021
    Date of Patent: May 28, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Ming-Chih Yew, Shu-Shen Yeh, Chin-Hua Wang, Po-Yao Lin, Shin-Puu Jeng
  • Patent number: 11996321
    Abstract: A method includes forming a conductive feature through a first dielectric layer, sequentially forming a second dielectric layer and a third dielectric layer over the first dielectric layer, and etching the third dielectric layer to form an opening. A first width of the opening at a top surface of the third dielectric layer is greater than a second width of the opening at a first interface between the third dielectric layer and the second dielectric layer. The method also includes etching the second dielectric layer until the opening extends to the conductive feature, thereby forming an enlarged opening, and forming a metal material in the enlarged opening. A third width of the enlarged opening at the first interface is equal to or less than a fourth width of the enlarged opening at a second interface between the second dielectric layer and the first dielectric layer.
    Type: Grant
    Filed: June 17, 2021
    Date of Patent: May 28, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Te-Chih Hsiung, Jyun-De Wu, Yi-Chun Chang, Yi-Chen Wang, Yuan-Tien Tu
  • Patent number: 11996345
    Abstract: A package structure includes a first semiconductor die, a first insulating encapsulation, a thermal coupling structure, and a heat dissipating component thermally coupled to the first semiconductor die through the thermal coupling structure. The first semiconductor die includes an active side, a rear side, and a sidewall connected to the active side and the rear side. The first insulating encapsulation extends along the sidewall of the first semiconductor die and includes a first side substantially leveled with the active side, a second side opposite to the first side, and topographic features at the second side. The thermal coupling structure includes a metallic layer overlying and the rear side of the first semiconductor die and the topographic features of the first insulating encapsulation. A manufacturing method of a package structure is also provided.
    Type: Grant
    Filed: August 27, 2021
    Date of Patent: May 28, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chih-Hao Chen, Po-Yuan Cheng, Pu Wang, Li-Hui Cheng, Szu-Wei Lu
  • Patent number: 11997677
    Abstract: Methods, systems, and devices for wireless communications are described. A user equipment (UE) may monitor a first control resource pool associated with sidelink control signaling during a first sensing window and monitor a portion of a second resource pool associated with sidelink data signaling during a second sensing window. The UE may perform joint resource selection on the first resource pool and the second resource pool based on the monitoring during the first and second sensing windows. The UE may transmit a sidelink control information message including resource indication fields to reserve the selected sidelink control channel resources and selected sidelink shared channel resources. The UE may transmit the sidelink data message on one or more of the reserved sidelink shared channel resources.
    Type: Grant
    Filed: October 8, 2021
    Date of Patent: May 28, 2024
    Assignee: QUALCOMM Incorporated
    Inventors: Chih-Hao Liu, Jing Sun, Yisheng Xue, Xiaoxia Zhang, Xiaojie Wang, Sony Akkarakaran, Ozcan Ozturk, Piyush Gupta, Tao Luo
  • Patent number: 11996165
    Abstract: A memory chip includes a first decoding device and a memory device. The first decoding device is configured to generate multiple word line signals. The memory device is configured to generate a third data signal based on a first data signal and a second data signal. The memory device includes a first memory circuit and a second memory circuit. The first memory circuit is configured to generate the first data signal at a first node according to the word line signals during a first period. The second memory circuit is configured to generate the second data signal at a second node different from the first node according to the word line signals during a second period after the first period. A method of operating a memory chip is also disclosed herein.
    Type: Grant
    Filed: May 17, 2022
    Date of Patent: May 28, 2024
    Assignee: AU OPTRONICS CORPORATION
    Inventors: Hsiang-Chi Cheng, Shyh-Bin Kuo, Yi-Cheng Lai, Chung-Hung Chen, Shih-Hsien Yang, Yu-Chih Wang, Kuo-Hsiang Chen
  • Publication number: 20240168088
    Abstract: A voltage detection device includes a voltage divider circuit, a comparator circuit and a switch control circuit. The voltage divider circuit operates in a first mode based on a switching signal and divides a power voltage to generate an input voltage. The comparator circuit compares the input voltage with a set of reference voltages to generate a detection signal. The switch control circuit selectively adjusts a switching signal according to the detection signal after a predetermined period has elapsed from power-on of the power voltage so as to control the voltage divider circuit to switch from operating in the first mode to operating in a second mode. The first mode corresponds to a first target level of the power voltage, the second mode corresponds to a second target level of the power voltage, and the first target level is higher than the second target level.
    Type: Application
    Filed: October 31, 2023
    Publication date: May 23, 2024
    Inventors: Wei-Ping WANG, Wei-Chih CHENG, Yen-Ping LIU
  • Patent number: 11990390
    Abstract: A semiconductor structure is provided, including: a substrate and a dielectric layer arranged on the substrate; a conductive plug, wherein a first part of the conductive plug is arranged in the substrate, and a second part of the conductive plug is arranged in the dielectric layer; and an isolation ring structure at least surrounding the second part of the conductive plug.
    Type: Grant
    Filed: August 30, 2021
    Date of Patent: May 21, 2024
    Assignee: Changxin Memory Technologies, Inc.
    Inventors: Ping-Heng Wu, Chih-Wei Chang, Hailin Wang
  • Patent number: 11989335
    Abstract: A processing circuit including a first oscillation circuit, a second oscillation circuit, a counting circuit, and a control circuit is provided. The first oscillation circuit receives an input voltage and generates a first clock signal according to the input voltage. The second oscillation circuit receives an output voltage and generates a second clock signal according to the output voltage. The counting circuit receives the output voltage. The counting circuit adjusts a first counter value according to the first clock signal and adjusts a second counter value according to the second clock signal. The control circuit receives the output voltage and determines whether the input voltage is experiencing an attack according to the first counter value and the second counter value. The first oscillation circuit operates in an un-protected power domain. The second oscillation circuit, the counting circuit, and the control circuit operate in a protected power domain.
    Type: Grant
    Filed: December 30, 2020
    Date of Patent: May 21, 2024
    Assignee: NUVOTON TECHNOLOGY CORPORATION
    Inventor: Cheng-Chih Wang
  • Patent number: 11990429
    Abstract: A method includes bonding a second package component to a first package component, bonding a third package component to the first package component, attaching a dummy die to the first package component, encapsulating the second package component, the third package component, and the dummy die in an encapsulant, and performing a planarization process to level a top surface of the second package component with a top surface of the encapsulant. After the planarization process, an upper portion of the encapsulant overlaps the dummy die. The dummy die is sawed-through to separate the dummy die into a first dummy die portion and a second dummy die portion. The upper portion of the encapsulant is also sawed through.
    Type: Grant
    Filed: November 28, 2022
    Date of Patent: May 21, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chih-Wei Wu, Ying-Ching Shih, Kung-Chen Yeh, Li-Chung Kuo, Pu Wang, Szu-Wei Lu
  • Publication number: 20240164203
    Abstract: Provided is an OLED having an anode, a cathode and an organic emissive layer disposed between the anode and the cathode.
    Type: Application
    Filed: November 16, 2023
    Publication date: May 16, 2024
    Applicant: Universal Display Corporation
    Inventors: Chun LIN, Zhiqiang JI, Ting-Chih WANG, Pierre-Luc T. BOUDREAULT
  • Publication number: 20240157496
    Abstract: A method for facilitating analysis of causes of machining defects is provided. The method is carried out by a computer system. The method includes the step of obtaining motion data and vibration acceleration data about the tip of a cutter mounted on a machine tool. The method further includes the step of obtaining time-frequency information about the vibration acceleration data by performing a time-frequency analysis on the vibration acceleration data. The method further includes the step of obtaining vibration-displacement data by normalizing the time-frequency information. The method further includes the step of obtaining amplitude-distribution data about the tip by synchronizing the motion data and the vibration-displacement data.
    Type: Application
    Filed: December 19, 2022
    Publication date: May 16, 2024
    Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
    Inventors: Chun-Ting CHEN, Jheng-Jie LIN, Chien-Chih LIAO, Jen-Ji WANG
  • Publication number: 20240162065
    Abstract: A method of determining an operational status of a semiconductor manufacturing assembly uses internal vibrations of an in-situ assembly to detect defects. The method may include initiating a first test vibration in an internal structure of the semiconductor manufacturing assembly while the semiconductor manufacturing assembly is in-situ in a semiconductor processing chamber, receiving a first vibration signal caused by the first test vibration, transforming the first vibration signal into a first frequency domain representation of the first vibration signal, determining the operational status of the semiconductor manufacturing assembly based on the first frequency domain representation, and performing a corrective action for the semiconductor manufacturing assembly in response to the operational status.
    Type: Application
    Filed: November 15, 2022
    Publication date: May 16, 2024
    Inventors: Yao-Hung YANG, Chih-Yang CHANG, Shannon WANG
  • Patent number: 11984381
    Abstract: A semiconductor package structure is provided. The semiconductor package structure includes a carrier substrate, an interposer substrate, a semiconductor device, a lid, and a thermal interface material. The interposer substrate is disposed on the carrier substrate. The semiconductor device is disposed on the interposer substrate. The lid is disposed on the carrier substrate to cover the semiconductor device. The thermal interface material is disposed between the lid and the semiconductor device. A first recess is formed on a lower surface of the lid facing the semiconductor device, and the first recess overlaps the semiconductor device in a top view.
    Type: Grant
    Filed: November 16, 2021
    Date of Patent: May 14, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Po-Chen Lai, Ming-Chih Yew, Po-Yao Lin, Chin-Hua Wang, Shin-Puu Jeng
  • Publication number: 20240152194
    Abstract: A power consumption reduction method can include defining y operation scenarios according to x types of extracted information, generating z power profiles each used for controlling power provided to a subset of a plurality of processors, assigning the z power profiles to the y operation scenarios in a machine learning model, collecting to-be-evaluated information by the plurality of processors, comparing the to-be-evaluated information with the x types of extracted information to find a most similar type of extracted information, using the machine learning model to select an optimal power profile from the z power profiles according to the most similar type of extracted information, and applying the optimal power profile to control the power provided to the subset of the plurality of processors. The subset of the plurality of processors are of the same type of processor. x, y and z can be an integer larger than zero.
    Type: Application
    Filed: August 18, 2023
    Publication date: May 9, 2024
    Applicant: MEDIATEK INC.
    Inventors: Wen-Wen Hsieh, Ying-Yi Teng, Chien-Chih Wang
  • Publication number: 20240155292
    Abstract: An electronic device includes two speakers, a single functional chip, a parameter extraction circuit, an audio processing module, a gain adjusting circuit and a current detecting unit. The current detecting unit is disposed in the functional chip for detecting the driving current of the two speakers. The functional chip provides the driving voltage of the two speakers based on an output signal and converts the analogue current/voltages of the two speakers into digital current/voltages. The parameter extraction circuit acquires the parameter of each speaker based on the digital current/voltages. The audio processing module acquires the gains of various physical quantities based on the parameter of each speaker and determines the final gain of each physical quantity. The gain adjusting circuit provides the output signal by adjusting the gain of an input signal based on the final gain of each physical quantity.
    Type: Application
    Filed: December 12, 2022
    Publication date: May 9, 2024
    Applicant: RICHTEK TECHNOLOGY CORP.
    Inventors: Tsung-Han Yang, Yen-Chih Wang, Ming-Jun Hsiao, Tsung-Nan Wu
  • Publication number: 20240152649
    Abstract: The disclosure provides a data privacy protection method, a server device, and a client device for federated learning. A public dataset is used to perform model training on a machine learning model by a server device to generate a gradient pool including multiple first gradients. The gradient pool and the machine learning model are received by a client device. The client device uses a local dataset to perform model training on the machine learning model to obtain a second gradient. A local gradient is selected from the first gradients in the gradient pool according to the second gradient using a differential privacy algorithm by the client device. An aggregated machine learning model is generated by performing model aggregation based on the local gradient by the server device.
    Type: Application
    Filed: December 8, 2022
    Publication date: May 9, 2024
    Applicant: Industrial Technology Research Institute
    Inventors: Ming-Chih Kao, Pang-Chieh Wang, Chia Mu Yu, Kang Cheng Chen