Abstract: A semiconductor device includes a substrate. The semiconductor device also includes a semiconductor layer disposed in the substrate. The semiconductor device further includes a first dielectric layer disposed on the semiconductor layer. The semiconductor device includes a second dielectric layer disposed on the first dielectric layer. The semiconductor device also includes a pair of thermopile segments disposed on the second dielectric layer. The first dielectric layer and the second dielectric layer form a chamber.

Abstract: A handwriting data processing method is applied to a pen display having wireless communication function and a data processing device. The handwriting data processing method includes the steps of: the data processing device obtaining a handwriting data from the pen display in a wireless communication manner; the data processing device generating a compressed screen image and transmitting the data of the compressed screen image and the handwriting data, which is not compressed, to the pen display in the wireless communication manner; the pen display uncompressing the data of the compressed screen image and overlapping the uncompressed screen image and the handwriting data to form a complete screen image and displaying the complete screen image. By the handwriting processing method, the machine time of the processor of the pen display is effectively lowered, significantly reducing the delay phenomenon of the displayed handwriting.

Abstract: In an embodiment, a device includes a substrate, a first semiconductor layer that extends from the substrate, and a second semiconductor layer on the first semiconductor layer. The first semiconductor layer includes silicon and the second semiconductor layer includes silicon germanium, with edge portions of the second semiconductor layer having a first germanium concentration, a center portion of the second semiconductor layer having a second germanium concentration, and the second germanium concentration being less than the first germanium concentration. The device also includes a gate stack on the second semiconductor layer, lightly doped source/drain regions in the second semiconductor layer, and source and drain regions extending into the lightly doped source/drain regions.

Abstract: In an embodiment, a device includes a substrate, a first semiconductor layer that extends from the substrate, and a second semiconductor layer on the first semiconductor layer. The first semiconductor layer includes silicon and the second semiconductor layer includes silicon germanium, with edge portions of the second semiconductor layer having a first germanium concentration, a center portion of the second semiconductor layer having a second germanium concentration, and the second germanium concentration being less than the first germanium concentration. The device also includes a gate stack on the second semiconductor layer, lightly doped source/drain regions in the second semiconductor layer, and source and drain regions extending into the lightly doped source/drain regions.

Abstract: A semiconductor structure is provided. The semiconductor structure includes a gate structure over a fin structure, and a source/drain structure in the fin structure and adjacent to the gate structure. The source/drain structure includes: a first epitaxial layer over the fin structure, a second epitaxial layer over the first epitaxial layer, and an epitaxial capping layer over the second epitaxial layer. The semiconductor structure also includes a silicide layer formed in contact with the source/drain structure. The silicide layer has a curved bottom surface, and the curved bottom surface of the silicide layer intersects with the second epitaxial layer and the epitaxial capping layer.

Abstract: In an embodiment, a method of forming a semiconductor device includes forming a fin protruding above a substrate; forming a gate structure over the fin; forming a recess in the fin and adjacent to the gate structure; performing a wet etch process to clean the recess; treating the recess with a plasma process; and performing a dry etch process to clean the recess after the plasma process and the wet etch process.

Abstract: A semiconductor structure is provided. The semiconductor structure includes a gate structure, a first source/drain structure, and a contact structure. The gate structure has a gate dielectric layer over a first fin structure. The first source/drain structure is positioned in the first fin structure and adjacent to the gate structure. The first source/drain structure includes a first epitaxial layer in contact with the top surface of the first fin structure and a second epitaxial layer over the first epitaxial layer and extending above a bottom surface of the gate dielectric layer. The contact structure extends into the first source/drain structure. The top surface of the first fin structure is between a top surface and a bottom surface of the first source/drain structure.

Abstract: In an embodiment, a method of forming a semiconductor device includes forming a fin protruding above a substrate; forming a gate structure over the fin; forming a recess in the fin and adjacent to the gate structure; performing a wet etch process to clean the recess; treating the recess with a plasma process; and performing a dry etch process to clean the recess after the plasma process and the wet etch process.

Abstract: The disclosure discloses an object positioning method and system. The object positioning method includes: acquiring an original object image including a to-be-positioned object; demagnifying the original object image; inputting a demagnified object image to a rough-positioning model for identification, to determine a plurality of rough feature positions; acquiring a plurality of image blocks from the original object image according to the rough feature positions; inputting the image blocks to a precise-positioning model for identification, to determine a plurality of precise feature positions; and determining a position of the to-be-positioned object in the original object image.

Abstract: A semiconductor device includes a gate structure formed over a channel region of the semiconductor device, a source/drain region adjacent the channel region, and an electrically conductive contact layer over the source/drain region. The source/drain region includes a first epitaxial layer having a first material composition and a second epitaxial layer formed over the first epitaxial layer. The second epitaxial layer has a second material composition different from the first composition. The electrically conductive contact layer is in contact with the first and second epitaxial layers. A bottom of the electrically conductive contact layer is located below an uppermost portion of the first epitaxial layer.

Abstract: A semiconductor device includes a gate structure formed over a channel region of the semiconductor device, a source/drain region adjacent the channel region, and an electrically conductive contact layer over the source/drain region. The source/drain region includes a first epitaxial layer having a first material composition and a second epitaxial layer formed over the first epitaxial layer. The second epitaxial layer has a second material composition different from the first composition. The electrically conductive contact layer is in contact with the first and second epitaxial layers. A bottom of the electrically conductive contact layer is located below an uppermost portion of the first epitaxial layer.

Abstract: In an embodiment, a device includes: a substrate; a first semiconductor layer extending from the substrate, the first semiconductor layer including silicon; a second semiconductor layer on the first semiconductor layer, the second semiconductor layer including silicon germanium, edge portions of the second semiconductor layer having a first germanium concentration, a center portion of the second semiconductor layer having a second germanium concentration, the second germanium concentration being less than the first germanium concentration, the edge portions of the second semiconductor layer including sides and a top surface of the second semiconductor layer; a gate stack on the second semiconductor layer; lightly doped source/drain regions in the second semiconductor layer, the lightly doped source/drain regions being adjacent the gate stack; and source and drain regions extending into the lightly doped source/drain regions.

Abstract: In an embodiment, a method of forming a semiconductor device includes forming a fin protruding above a substrate; forming a gate structure over the fin; forming a recess in the fin and adjacent to the gate structure; performing a wet etch process to clean the recess; treating the recess with a plasma process; and performing a dry etch process to clean the recess after the plasma process and the wet etch process.

Abstract: In an embodiment, a method of forming a semiconductor device includes forming a fin protruding above a substrate; forming a gate structure over the fin; forming a recess in the fin and adjacent to the gate structure; performing a wet etch process to clean the recess; treating the recess with a plasma process; and performing a dry etch process to clean the recess after the plasma process and the wet etch process.

Abstract: In an embodiment, a device includes: a substrate; a first semiconductor layer extending from the substrate, the first semiconductor layer including silicon; a second semiconductor layer on the first semiconductor layer, the second semiconductor layer including silicon germanium, edge portions of the second semiconductor layer having a first germanium concentration, a center portion of the second semiconductor layer having a second germanium concentration, the second germanium concentration being less than the first germanium concentration, the edge portions of the second semiconductor layer including sides and a top surface of the second semiconductor layer; a gate stack on the second semiconductor layer; lightly doped source/drain regions in the second semiconductor layer, the lightly doped source/drain regions being adjacent the gate stack; and source and drain regions extending into the lightly doped source/drain regions.

Abstract: A semiconductor structure is provided. The semiconductor structure includes a gate structure, a first source/drain structure, and a contact structure. The gate structure has a gate dielectric layer over a first fin structure. The first source/drain structure is positioned in the first fin structure and adjacent to the gate structure. The first source/drain structure includes a first epitaxial layer in contact with the top surface of the first fin structure and a second epitaxial layer over the first epitaxial layer and extending above a bottom surface of the gate dielectric layer. The contact structure extends into the first source/drain structure. The top surface of the first fin structure is between a top surface and a bottom surface of the first source/drain structure.

Abstract: A semiconductor structure and a method for forming the same are provided. The semiconductor structure includes a gate structure, a first source/drain structure, and a contact structure. The gate structure has a gate dielectric layer over a first fin structure. The first source/drain structure is positioned in the first fin structure and adjacent to the gate structure. The first source/drain structure includes a first epitaxial layer in contact with the top surface of the first fin structure and a second epitaxial layer over the first epitaxial layer and extending above a bottom surface of the gate dielectric layer. The contact structure extends into the first source/drain structure. The top surface of the first fin structure is between a top surface and a bottom surface of the first source/drain structure.

Abstract: The present disclosure describes a method to form silicon germanium (SiGe) source/drain regions with the incorporation of a lateral etch in the epitaxial source/drain growth process. For example, the method can include forming a plurality of fins on a substrate, where each of the plurality of fins has a first width. The SiGe source/drain regions can be formed on the plurality of fins, where each SiGe source/drain region has a second width in a common direction with the first width and a height. The method can also include selectively etching—e.g., via a lateral etch—the SiGe source/drain regions to decrease the second width of the SiGe source/drain regions. By decreasing the width of the SiGe source/drain regions, electrical shorts between neighboring fins can be prevented or minimized. Further, the method can include growing an epitaxial capping layer over the Si/Ge source/drain regions.

Abstract: In an embodiment, a method of forming a semiconductor device includes forming a fin protruding above a substrate; forming a gate structure over the fin; forming a recess in the fin and adjacent to the gate structure; performing a wet etch process to clean the recess; treating the recess with a plasma process; and performing a dry etch process to clean the recess after the plasma process and the wet etch process.

Abstract: In an embodiment, a device includes: a substrate; a first semiconductor layer extending from the substrate, the first semiconductor layer including silicon; a second semiconductor layer on the first semiconductor layer, the second semiconductor layer including silicon germanium, edge portions of the second semiconductor layer having a first germanium concentration, a center portion of the second semiconductor layer having a second germanium concentration, the second germanium concentration being less than the first germanium concentration, the edge portions of the second semiconductor layer including sides and a top surface of the second semiconductor layer; a gate stack on the second semiconductor layer; lightly doped source/drain regions in the second semiconductor layer, the lightly doped source/drain regions being adjacent the gate stack; and source and drain regions extending into the lightly doped source/drain regions.