Patents by Inventor An-Chun Chen

An-Chun Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Integrated circuit device with improved layout
    Patent number: 10903239
    Abstract: An integrated circuit device includes a device layer having devices spaced in accordance with a predetermined device pitch, a first metal interconnection layer disposed above the device layer and coupled to the device layer, and a second metal interconnection layer disposed above the first metal interconnection layer and coupled to the first metal interconnection layer through a first via layer. The second metal interconnection layer has metal lines spaced in accordance with a predetermined metal line pitch, and a ratio of the predetermined metal line pitch to predetermined device pitch is less than 1.
    Type: Grant
    Filed: July 25, 2018
    Date of Patent: January 26, 2021
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Fong-yuan Chang, Chun-Chen Chen, Po-Hsiang Huang, Lee-Chung Lu, Chung-Te Lin, Jerry Chang Jui Kao, Sheng-Hsiung Chen, Chin-Chou Liu
  • Compact vertical injection punch through floating gate analog memory and a manufacture thereof
    Patent number: 10896979
    Abstract: A vertical injection punchthrough based metal oxide semiconductor (VIPMOS) device and method of manufacturing the same, include a control gate, an erase gate, a floating gate, and an active area where the control gate, the erase gate, and the floating gate are coplanar and perpendicular to the active area.
    Type: Grant
    Filed: September 28, 2017
    Date of Patent: January 19, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Effendi Leobandung, Yulong Li, Tak Ning, Paul Michael Solomon, Chun-Chen Yeh
  • Recommendation method implemented in electronic device
    Patent number: 10895960
    Abstract: An electronic device includes a communication port, a display, a processor, and a memory. The processor detects whether an external device plugs into the communication port, displays a user interface on the display when an external device plugs into the communication port, detects whether the user interface receives a predetermined user operation, recommends relevant data linked to the external device according to predetermined rules when the user interface receives the predetermined user operation, and displays the relevant data linked to the external device on the display.
    Type: Grant
    Filed: May 7, 2019
    Date of Patent: January 19, 2021
    Assignee: Mobile Drive Technology Co., Ltd.
    Inventors: Yu-Chun Chen, Cheng-Kuo Yang, Mu-Ann Chen, Ke-Chien Chou
  • SEMICONDUCTOR DEVICE PACKAGE AND METHOD OF MANUFACTURING THE SAME
    Publication number: 20210013585
    Abstract: A semiconductor device package includes a substrate and an antenna module. The substrate has a first surface and a second surface opposite to the first surface. The antenna module is disposed on the first surface of the substrate with a gap. The antenna module has a support and an antenna layer. The support has a first surface facing away from the substrate and a second surface facing the substrate. The antenna layer is disposed on the first surface of the support. The antenna layer has a first antenna pattern and a first dielectric layer.
    Type: Application
    Filed: July 9, 2019
    Publication date: January 14, 2021
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Cheng-Lin Ho, Chih-Cheng Lee, Chun Chen Chen, Yuanhao Yu
  • Ocular optical system
    Patent number: 10890696
    Abstract: An ocular optical system configured to allow imaging rays from a display frame to enter an observer's eye through the ocular optical system to form an image is provided. The ocular optical system includes a lens element having an eye-side surface and a display-side surface. The lens element has an optical axis extending from a display side toward an eye side. The display-side surface of the lens element adopts a Fresnel lens design. The ocular optical system satisfies: 4.317?EFL/T1?12.463, where EFL represents an effective focal length of the ocular optical system, and T1 represents a thickness of the lens element on the optical axis.
    Type: Grant
    Filed: December 3, 2019
    Date of Patent: January 12, 2021
    Assignee: GENIUS ELECTRONIC OPTICAL CO., LTD.
    Inventors: Chun-Yang Huang, Wan-Chun Chen
  • METHOD OF DESIGNING SEMICONDUCTOR DEVICE
    Publication number: 20210004517
    Abstract: A method including selecting a plurality of layout patterns, wherein each of the layout patterns comprises a corresponding via pillar structure that satisfies an electromigration (EM) rule, wherein each of the via pillar structures comprises metal layers and at least one via coupled to the metal layers. The method further includes selecting a layout pattern from the plurality of layout patterns having a smallest physical size. The method further includes performing a placement and routing process by using the selected layout pattern.
    Type: Application
    Filed: September 23, 2020
    Publication date: January 7, 2021
    Inventors: Shao-Huan WANG, Sheng-Hsiung CHEN, Wen-Hao CHEN, Chun-Chen CHEN, Hung-Chih OU
  • THERMAL HEAD STRUCTURE CAPABLE OF IMPROVING PRINTING RESOLUTION AND MANUFACTURING METHOD THEREOF
    Publication number: 20210001640
    Abstract: A manufacturing method of a thermal head structure capable of improving printing resolution includes the following steps. A heat storing layer, a first electrode pattern, a heat generating resistor layer, a second electrode pattern and an insulating protective layer are formed to be overlapped on a substrate, and the step of forming the heat generating resistor layer is between the step of forming the first electrode pattern and the step of forming the second electrode pattern chronologically.
    Type: Application
    Filed: June 1, 2020
    Publication date: January 7, 2021
    Inventors: Ming-Jia LI, Yi-Wei LIN, Chun-Chen CHEN
  • Semiconductor device package, electronic assembly and method for manufacturing the same
    Patent number: 10886208
    Abstract: A semiconductor device package includes a carrier, an electronic component, a connection element and an encapsulant. The electronic component is disposed on a surface of the carrier. The connection element is disposed on the surface and adjacent to an edge of the carrier. The encapsulant is disposed on the surface of the carrier. A portion of the connection element is exposed from an upper surface and an edge of the encapsulant.
    Type: Grant
    Filed: January 31, 2019
    Date of Patent: January 5, 2021
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Cheng-Lin Ho, Chih-Cheng Lee, Chun Chen Chen, Chen Yuang Chen
  • Face identification system and face identification method with high security level and low power consumption
    Patent number: 10885314
    Abstract: A face identification system includes a transmitter, a receiver, a database, an artificial intelligence chip, and a main processor. The transmitter is used for emitting at least one first light signal to an object. The receiver is used for receiving at least one second light signal reflected by the object. The database is used for saving training data. The artificial intelligence chip is coupled to the transmitter, the receiver, and the database for identifying a face image from the object according to the at least one second light signal and the training data. The main processor is coupled to the artificial intelligence chip for receiving a face identification signal generated from the artificial intelligence chip.
    Type: Grant
    Filed: January 22, 2018
    Date of Patent: January 5, 2021
    Assignee: Kneron Inc.
    Inventor: Chun-Chen Liu
  • TWO-DIMENSIONAL (2D) SELF-ALIGNED CONTACT (OR VIA) TO ENABLE FURTHER DEVICE SCALING
    Publication number: 20200411376
    Abstract: 2D self-aligned contact structures (both gate contact and source/drain contact) are provided that can improve the process control and push further scaling. The 2D self-aligned contact structures can enable tighter process control which can lead to further device scaling. In accordance with the present application, the gate contact structure is confined in one direction by a sacrificial spacer structure that is present in a dielectric material layer, and in another direction by an edge of a metallization structure that is located above the gate contact structure.
    Type: Application
    Filed: June 28, 2019
    Publication date: December 31, 2020
    Inventors: Junli Wang, Veeraraghavan S. Basker, Chun-Chen Yeh, Alexander Reznicek
  • DISPLAY APPARATUS
    Publication number: 20200411561
    Abstract: A display apparatus includes a wireless transmission unit and a display panel. The display panel includes a substrate, a plurality of pixel units and a signal line. The substrate includes a display region and a periphery region. The periphery region surrounds the display region. The pixel units are disposed on the display region. Each of the pixel units includes an active device and a pixel electrode. The active device is electrically connected to the pixel electrode. The signal line is on the periphery region. As viewed from a top view, the signal line has an annular shape having a gap and surrounds the display region.
    Type: Application
    Filed: June 22, 2020
    Publication date: December 31, 2020
    Inventors: Chia-Chi CHANG, Chih-Chun CHEN, Chi-Ming WU, Yi-Ching WANG, Jia-Hung CHEN, Bo-Tsang HUANG, Wei-Yueh KU
  • TRANSISTORS WITH UNIFORM SOURCE/DRAIN EPITAXY
    Publication number: 20200403099
    Abstract: A method for manufacturing a semiconductor device includes forming a plurality of semiconductor layers on a semiconductor substrate, and forming a plurality of gate structures spaced apart from each other on the semiconductor layers. The semiconductor layers are patterned into a plurality of patterned stacks spaced apart from each other, wherein the plurality of patterned stacks are under the plurality of gate structures. The method also includes forming a plurality of sacrificial spacers on lateral sides of the plurality of gate structures, and growing a plurality of source/drain regions. The source/drain regions are adjacent the patterned stacks and include a plurality of pillar portions formed on lateral sides of the sacrificial spacers. The sacrificial spacers and the plurality of pillar portions are removed.
    Type: Application
    Filed: June 19, 2019
    Publication date: December 24, 2020
    Inventors: Kangguo Cheng, Ruilong Xie, Chun-Chen Yeh, Tenko Yamashita
  • Embedded non-volatile memory device and fabrication method of the same
    Patent number: 10872898
    Abstract: Systems and methods of forming such include method, forming a memory gate (MG) stack in a first region, forming a sacrificial polysilicon gate on a high-k dielectric in a second region, wherein the first and second regions are disposed in a single substrate. Then a select gate (SG) may be formed adjacent to the MG stack in the first region of the semiconductor substrate. The sacrificial polysilicon gate may be replaced with a metal gate to form a logic field effect transistor (FET) in the second region. The surfaces of the substrate in the first region and the second region are substantially co-planar.
    Type: Grant
    Filed: December 20, 2017
    Date of Patent: December 22, 2020
    Assignee: Cypress Semiconductor Corporation
    Inventors: Chun Chen, James Pak, Unsoon Kim, Inkuk Kang, Sung-Taeg Kang, Kuo Tung Chang
  • DEVICE AND METHOD FOR MANUFACTURING THE SAME
    Publication number: 20200395275
    Abstract: A device includes a die paddle and a plurality of leads. The leads surround the die paddle. Each of the leads includes an inner lead portion adjacent to and spaced apart from the die paddle, an outer lead portion opposite to the inner lead portion and a bridge portion between the inner lead portion and the outer lead portion. The inner lead portion has an upper bond section connected to the bridge portion and a lower support section below the upper bond section. A sum of a thickness of the upper bond section and a thickness of the lower support section is greater than a thickness of the bridge portion.
    Type: Application
    Filed: June 14, 2019
    Publication date: December 17, 2020
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Kuang-Hsiung CHEN, Chih-Hung HSU, Mei-Lin HSIEH, Yi-Cheng HSU, Yuan-Chun CHEN, Yu-Shun HSIEH, Ko-Pu WU
  • Cover system
    Patent number: 10863787
    Abstract: A method and apparatus can include: providing a cover, the cover including face cover, neck cover, crown cover, side cover, and back cover; creating a cover opening in the cover above the face cover for exposure of facial features of a user from the cover; attaching a helmet cover at an attachment point near the back cover configured to expand around a helmet; and forming a helmet cover opening.
    Type: Grant
    Filed: February 15, 2017
    Date of Patent: December 15, 2020
    Inventors: Li Ray Chen, Shih-Chun Chen
  • Logic cell structure and integrated circuit with the logic cell structure
    Patent number: 10868538
    Abstract: A logic cell structure includes: a first portion, with a first height, arranged to be a first layout of a first semiconductor element; a second portion, with the first height, arranged to be a second layout of a second semiconductor element, wherein the first portion is separated from the second portion; and a third portion arranged to be a third layout of an interconnecting path used for coupling the first semiconductor element and the second semiconductor element.
    Type: Grant
    Filed: July 29, 2019
    Date of Patent: December 15, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Shao-Huan Wang, Chun-Chen Chen, Sheng-Hsiung Chen, Kuo-Nan Yang
  • Maltooligosyl trehalose synthase mutant with improved thermal stability
    Patent number: 10865405
    Abstract: The present disclosure discloses a maltooligosyl trehalose synthase mutant with improved thermal stability, and belongs to the technical fields of enzyme engineering and protein engineering. The residual enzyme activities of the MTSase mutants S361R, S444E, S361R/S444E, S361K/S444E, G415P/S361R/S444E and G415P consistent with the present disclosure after treatment at 60° C. for 10 min are respectively 70.3%, 50.1%, 83.5%, 65.9%, 100% and 80.7%, which are respectively 1.6, 1.1, 1.9, 1.5, 2.3 and 1.9 times of that of the wild type. The half-lives of the S361R/S444E and G415P/S361R/S444E at 60° C. are respectively 14.9 min and 90.8 min which are respectively 3.2 and 19.7 times of that of the wild type, indicating that the thermal stability of the MTSase mutant consistent with the present disclosure is significantly improved than that of the wild type.
    Type: Grant
    Filed: May 30, 2019
    Date of Patent: December 15, 2020
    Assignee: JIANGNAN UNIVERSITY
    Inventors: Jing Wu, Lingqia Su, Chun Chen, Zirui Wang, Jinyun Feng
  • Composite spacer enabling uniform doping in recessed fin devices
    Patent number: 10854733
    Abstract: A semiconductor device that includes at least one fin structure and a gate structure present on a channel portion of the fin structure. An epitaxial semiconductor material is present on at least one of a source region portion and a drain region portion on the fin structure. The epitaxial semiconductor material includes a first portion having a substantially conformal thickness on a lower portion of the fin structure sidewall and a second portion having a substantially diamond shape that is present on an upper surface of the source portion and drain portion of the fin structure. A spacer present on first portion of the epitaxial semiconductor material.
    Type: Grant
    Filed: April 19, 2018
    Date of Patent: December 1, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Veeraraghavan S. Basker, Zuoguang Liu, Tenko Yamashita, Chun-Chen Yeh
  • Wireless device
    Patent number: 10855108
    Abstract: A wireless device is provided and includes a coil assembly. The coil assembly includes a first coil, a second coil, a first contact, a second contact, and a third contact. The second coil is configured to be connected to the first coil in series. The first contact is configured to be connected to a first end of the first coil. The second contact is configured to be connected between the first coil and the second coil. The third contact is configured to be connected to a second end of the second coil. The first contact, the first coil and the second contact form a first circuit loop, and the first contact, the first coil, the second coil and the third contact form a second circuit loop.
    Type: Grant
    Filed: November 21, 2018
    Date of Patent: December 1, 2020
    Assignee: TDK Taiwan Corp.
    Inventors: Feng-Lung Chien, Mao-Chun Chen, Hsiang-Hui Hsu, Kuo-Jui Lee, Chien-Hung Lin
  • Real-time autofocus scanning
    Patent number: 10852523
    Abstract: Real-time autofocus. In an embodiment, a scanning apparatus includes an imaging sensor, a focusing sensor, an objective lens, and processor(s) configured to analyze image data captured by the imaging and focusing sensors, and move the objective lens. Real-time autofocus during scanning of a sample is achieved by determining a true-Z value for the objective lens for a point on a sample and for each of a plurality of regions on the sample. The true-Z values and/or surfaces calculated therefrom are used to determine a predicted-Z value for an unscanned region of the sample. The objective lens is adjusted to the predicted-Z value at the beginning of the unscanned region. After scanning the region, a true-Z value is determined for the region and compared to the predicted-Z value. A rescan of the region is initiated if the comparison exceeds a predetermined threshold.
    Type: Grant
    Filed: November 5, 2019
    Date of Patent: December 1, 2020
    Assignee: LEICA BIOSYSTEMS IMAGING, INC.
    Inventors: Leng-Chun Chen, Allen Olson, Yunlu Zou, Peyman Najmabadi, Greg Crandall