Patents by Inventor An-Cin Li

An-Cin Li has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12353768
    Abstract: A memory operation method, a memory storage device, and a memory control circuit unit are disclosed. The memory operation includes following steps. First data is received from a host system. The first data is stored into a first physical unit which is mapped to a first logical unit. In a first operation mode, a target calculation is performed based on the first data and second data stored in a second physical unit to obtain third data, and the third data is different from the first data. The third data is stored into a third physical unit which is also mapped to the first logical unit. The third data is transmitted to the host system.
    Type: Grant
    Filed: November 7, 2023
    Date of Patent: July 8, 2025
    Assignee: PHISON ELECTRONICS CORP.
    Inventors: Jian Ping Syu, Wei Lin, Szu-Wei Chen, An-Cin Li
  • Publication number: 20250123773
    Abstract: A memory operation method, a memory storage device, and a memory control circuit unit are disclosed. The memory operation includes following steps. First data is received from a host system. The first data is stored into a first physical unit which is mapped to a first logical unit. In a first operation mode, a target calculation is performed based on the first data and second data stored in a second physical unit to obtain third data, and the third data is different from the first data. The third data is stored into a third physical unit which is also mapped to the first logical unit. The third data is transmitted to the host system.
    Type: Application
    Filed: November 7, 2023
    Publication date: April 17, 2025
    Applicant: PHISON ELECTRONICS CORP.
    Inventors: Jian Ping Syu, Wei Lin, Szu-Wei Chen, An-Cin Li
  • Publication number: 20250060872
    Abstract: A data storage method, a host system, and a data storage system are disclosed. The method includes the following. An artificial intelligence (AI) model is executed. First data to be stored to a memory storage device is obtained. In response to the first data being generated by the AI model, second data is generated according to the first data, in which the second data includes the first data, and a data amount of the second data is greater than a data amount of the first data. A first write command is sent to the memory storage device according to the second data, so as to instruct the memory storage device to store the second data.
    Type: Application
    Filed: September 6, 2023
    Publication date: February 20, 2025
    Applicant: PHISON ELECTRONICS CORP.
    Inventors: Wei Lin, Jian Ping Syu, Szu-Wei Chen, An-Cin Li
  • Patent number: 12112808
    Abstract: A read voltage calibration method, a memory storage device, and a memory control circuit unit are provided. The read voltage calibration method includes: reading data from a first physical unit by using multiple read voltage levels; decoding the data to obtain multiple error evaluation parameters; determining a first vector distance parameter according to a first error evaluation parameter; determining multiple candidate read voltage levels according to the first vector distance parameter and a first read voltage level; determining a target read voltage level according to one of the candidate read voltage levels; and reading the data again from the first physical unit by using the target read voltage level.
    Type: Grant
    Filed: March 7, 2023
    Date of Patent: October 8, 2024
    Assignee: PHISON ELECTRONICS CORP.
    Inventors: Szu-Wei Chen, An-Cin Li, Yu-Hung Lin, Kai-Wei Tsou
  • Publication number: 20240249778
    Abstract: A read voltage calibration method, a memory storage device, and a memory control circuit unit are provided. The read voltage calibration method includes: reading data from a first physical unit by using multiple read voltage levels; decoding the data to obtain multiple error evaluation parameters; determining a first vector distance parameter according to a first error evaluation parameter; determining multiple candidate read voltage levels according to the first vector distance parameter and a first read voltage level; determining a target read voltage level according to one of the candidate read voltage levels; and reading the data again from the first physical unit by using the target read voltage level.
    Type: Application
    Filed: March 7, 2023
    Publication date: July 25, 2024
    Applicant: PHISON ELECTRONICS CORP.
    Inventors: Szu-Wei Chen, An-Cin Li, Yu-Hung Lin, Kai-Wei Tsou