Abstract: A solid-state imaging device having a protective wiring inserted between adjacent pixel pairs so that the generation of electrical charges caused by a voltage variation in adjacent pixel pairs may be restrained, and a method for manufacturing the same. A solid-state imaging device with an additional protective wiring may be provided between pixel pairs to restrain the generation of electric charges within one of the pixel pairs caused by a voltage variation in the other pixel pair. A method for manufacturing a solid-state imaging device with an additional protective wiring which is provided between pixel pairs to restrain the generation of electric charges within one of the pixel pairs caused by a voltage variation in the other pixel pair.

Abstract: Provided is an image sensor. According to embodiments, the subject image sensor can include a photodiode for converting incident light into electrical signals, a reset transistor for resetting a voltage value of a unit pixel, a drive transistor for providing an output voltage, a select transistor for selecting the unit pixel, a storage capacitor for storing electrons leaking from the photodiode, and a switching transistor for controlling the flow of charge to and from the storage capacitor. The switching transistor can be disposed connected to a node between the photodiode and the reset transistor, and the storage capacitor can be disposed at a side of the switching transistor.

Abstract: A capacitor may include at least one of a polysilicon layer over a semiconductor substrate; a capacitor dielectric layer over a polysilicon layer; an insulating layer over a capacitor dielectric layer; a metal layer connected to a capacitor dielectric layer through a first region of an insulating layer; an upper metal wiring layer connected to a metal layer over an insulating layer; and/or a lower metal wiring line layer connected to a polysilicon layer through a metal contact that passes through a second region of an insulating layer and a capacitor dielectric layer over the insulating layer.

Abstract: A capacitor may include at least one of a polysilicon layer over a semiconductor substrate; a capacitor dielectric layer over a polysilicon layer; an insulating layer over a capacitor dielectric layer; a metal layer connected to a capacitor dielectric layer through a first region of an insulating layer; an upper metal wiring layer connected to a metal layer over an insulating layer; and/or a lower metal wiring line layer connected to a polysilicon layer through a metal contact that passes through a second region of an insulating layer and a capacitor dielectric layer over the insulating layer.

Abstract: A capacitor may include at least one of a polysilicon layer over a semiconductor substrate; a capacitor dielectric layer over a polysilicon layer; an insulating layer over a capacitor dielectric layer; a metal layer connected to a capacitor dielectric layer through a first region of an insulating layer; an upper metal wiring layer connected to a metal layer over an insulating layer; and/or a lower metal wiring line layer connected to a polysilicon layer through a metal contact that passes through a second region of an insulating layer and a capacitor dielectric layer over the insulating layer.

Abstract: Provided is an image sensor. According to embodiments, the subject image sensor can include a photodiode for converting incident light into electrical signals, a reset transistor for resetting a voltage value of a unit pixel, a drive transistor for providing an output voltage, a select transistor for selecting the unit pixel, a storage capacitor for storing electrons leaking from the photodiode, and a switching transistor for controlling the flow of charge to and from the storage capacitor. The switching transistor can be disposed connected to a node between the photodiode and the reset transistor, and the storage capacitor can be disposed at a side of the switching transistor.

Abstract: A method for manufacturing a CIS reduces or prevents dark current in a photodiode region. In the method, a plurality of gates are formed on a semiconductor substrate, and impurities are implanted in side portions of a predetermined gate to form a photodiode region. Subsequently, a spacer nitride layer is formed and then etched to form a first spacer pattern covering the photodiode region and a second spacer pattern on sidewalls of the rest of the gates. After that, impurities are implanted using the first and second spacer patterns as a mask to form source/drain regions in portions of the semiconductor substrate that are exposed at the side portions of the gate(s). Subsequently, a salicide is formed on the gate and in the exposed portion of the semiconductor substrate.

Abstract: A capacitor may include at least one of a polysilicon layer over a semiconductor substrate; a capacitor dielectric layer over a polysilicon layer; an insulating layer over a capacitor dielectric layer; a metal layer connected to a capacitor dielectric layer through a first region of an insulating layer; an upper metal wiring layer connected to a metal layer over an insulating layer; and/or a lower metal wiring line layer connected to a polysilicon layer through a metal contact that passes through a second region of an insulating layer and a capacitor dielectric layer over the insulating layer.

Abstract: An apparatus for controlling a cache in a computing node, which is located between a node bus and an interconnection network to perform a cache coherence protocol, includes: a node bus interface for interfacing with the node bus; an interconnection network interface for interfacing with the interconnection network; a cache control logic means for controlling the cache to perform the cache coherence protocol; bus-side dual-port transaction buffers coupled between said node bus interface and said cache control logic means for buffering transaction requested and replied from or to local processors contained in the computing node; and network-side dual-port transaction buffers coupled between said interconnection network interface and said cache control logic for buffering transaction requested and replied from or to remote processors contained in another computing node coupled to the interconnection network.