Patents by Inventor An-Fang Lee

An-Fang Lee has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Pupil detection device
    Patent number: 10198631
    Abstract: There is provided a pupil tracking device including an active light source, an image sensor and a processing unit. The active light source emits light toward an eyeball alternatively in a first brightness value and a second brightness value. The image sensor captures a first brightness image corresponding to the first brightness value and a second brightness image corresponding to the second brightness value. The processing unit identifies a brightest region at corresponding positions of the first brightness image and the second brightness image as an active light image.
    Type: Grant
    Filed: August 31, 2016
    Date of Patent: February 5, 2019
    Assignee: PIXART IMAGING INC.
    Inventors: Yu-Hao Huang, Ming-Tsan Kao, Yi-Fang Lee, En-Feng Hsu, Meng-Huan Hsieh, Nien-Tse Chen
  • High voltage MOS structure and its manufacturing method
    Patent number: 10141398
    Abstract: A semiconductor structure includes a HV NMOS structure. The HV NMOS structure includes a source region, a drain region, a channel region, a gate dielectric, and a gate electrode. The source region and the drain region are separated from each other. The channel region is disposed between the source region and the drain region. The channel region has a channel direction from the source region toward the drain region. The gate dielectric is disposed on the channel region and on portions of the source region and the drain region. The gate electrode is disposed on the gate dielectric. The gate electrode includes a first portion of n-type doping and two second portions of p-type doping. The two second portions are disposed at two sides of the first portion. The two second portions have an extending direction perpendicular to the channel direction.
    Type: Grant
    Filed: December 18, 2017
    Date of Patent: November 27, 2018
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Ming-Hua Tsai, Jung Han, Chin-Chia Kuo, Wen-Fang Lee, Chih-Chung Wang
  • SEMICONDUCTOR STRUCTURES, MEMORY CELLS AND DEVICES COMPRISING FERROELECTRIC MATERIALS, SYSTEMS INCLUDING SAME, AND RELATED METHODS
    Publication number: 20180331113
    Abstract: A semiconductor structure includes an electrode, a ferroelectric material adjacent the electrode, the ferroelectric material comprising an oxide of at least one of hafnium and zirconium, the ferroelectric material doped with bismuth, and another electrode adjacent the ferroelectric material on an opposite side thereof from the first electrode. Related semiconductor structures, memory cells, semiconductor devices, electronic systems, and related methods are disclosed.
    Type: Application
    Filed: May 9, 2017
    Publication date: November 15, 2018
    Inventors: Albert Liao, Wayne I. Kinney, Yi Fang Lee, Manzar Siddik
  • Semiconductor structure and manufacturing method of the same
    Patent number: 10084083
    Abstract: A semiconductor structure and a manufacturing method of a semiconductor structure are provided. The semiconductor structure includes a semiconductor substrate, a gate, a first diffusion region and a second diffusion region. The gate is disposed on the semiconductor substrate and extends along a first direction. The first diffusion region is formed in the semiconductor substrate, and the second diffusion region is formed in the first diffusion region. The first diffusion region has a first portion located underneath the gate and a second portion protruded from a lateral side of the gate, the first portion has a first length parallel to the first direction, the second portion has a second length parallel to the first direction, and the first length is larger than the second length.
    Type: Grant
    Filed: October 17, 2017
    Date of Patent: September 25, 2018
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Shin-Hung Li, Kuan-Chuan Chen, Nien-Chung Li, Wen-Fang Lee, Chih-Chung Wang
  • SEMICONDUCTOR DEVICE
    Publication number: 20180233556
    Abstract: A semiconductor device including a substrate and a shallow trench isolation (STI) structure is provided. The substrate has a first voltage area and a second voltage area. A top surface of the substrate in the second voltage area is higher than a top surface of the substrate in the first voltage area, and a trench is defined in the substrate in between the first and second voltage area. The STI structure is located in the substrate within the trench, wherein a first portion of the STI structure is located in the first voltage area, a second portion of the STI structure is located in the second voltage area, and a step height difference exist in between a bottom surface of the first portion of the STI structure in the first voltage area and a bottom surface of the second portion of the STI structure in the second voltage area.
    Type: Application
    Filed: April 12, 2018
    Publication date: August 16, 2018
    Applicant: United Microelectronics Corp.
    Inventors: Chang-Po Hsiung, Ping-Hung Chiang, Shih-Chieh Pu, Chia-Lin Wang, Nien-Chung Li, Wen-Fang Lee, Shih-Yin Hsiao, Chih-Chung Wang
  • Method and system for selecting a communication interface
    Patent number: 10021609
    Abstract: The disclosure is related to a method and a system for selecting a communication interface. The method is applicable to a local area network including multiple access points. A main access point is first selected. The main access point acquires every access point's information within a local area network. The information relates to the access points that are in an idle state or not performing a critical task. A target antenna can be selected for performing a specific function. For example, the target antenna can be used to scan for the channels specified in dynamic frequency selection. After that, the scan result may result in changing channels. Through the above mechanism, the resources in every AP within the LAN can be adequately used, and the performance of wireless communication can be effectively improved.
    Type: Grant
    Filed: October 6, 2016
    Date of Patent: July 10, 2018
    Assignee: ARCADYAN TECHNOLOGY CORPORATION
    Inventor: Chih-Fang Lee
  • PUPIL DETECTION DEVICE
    Publication number: 20180160079
    Abstract: A pupil detection device includes an active light source, an image sensor and a processing unit. The active light source emits light toward an eyeball. The image sensor captures at least one image frame of the eyeball to be served as an image to be identified. The processing unit is configured to calculate a minimum gray value in the image to be identified and to identify a plurality of pixels surrounding the minimum gray value and having gray values within a gray value range as a pupil area.
    Type: Application
    Filed: February 1, 2018
    Publication date: June 7, 2018
    Inventors: Yu-Hao HUANG, Yi-Fang LEE, Ming-Tsan KAO, Meng-Huan HSIEH, En-Feng HSU, Nien-Tse CHEN
  • High-voltage metal-oxide-semiconductor transistor and fabrication method thereof
    Patent number: 9985129
    Abstract: A high-voltage MOS transistor includes a semiconductor substrate, a gate oxide layer on the semiconductor substrate, a gate on the gate oxide layer, a spacer covering a sidewall of the gate, a source on one side of the gate, and a drain on the other side of the gate. The gate includes at least a first discrete segment and a second discrete segment. The first discrete segment is not in direct contact with the second discrete segment. The spacer fills into a gap between the first discrete segment and the second discrete segment.
    Type: Grant
    Filed: November 22, 2017
    Date of Patent: May 29, 2018
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Shih-Yin Hsiao, Kuan-Liang Liu, Ching-Chung Yang, Kai-Kuen Chang, Ping-Hung Chiang, Nien-Chung Li, Wen-Fang Lee, Chih-Chung Wang
  • COMPOSITIONS AND METHODS FOR INHIBITING CD279 INTERACTIONS
    Publication number: 20180141975
    Abstract: Methods and compositions for inhibiting and/or interfering with interactions between (1) programmed Death-1 protein (also known as CD279) and (2) programmed death-ligand 1 (PD-L1) and/or programmed death-ligand 2 (PD-L2) are disclosed. In addition, methods and compositions for increasing IL-2 levels in a cell, and methods and compositions for preventing, treating, or ameliorating the effects of cancer in a subject, are disclosed.
    Type: Application
    Filed: December 9, 2016
    Publication date: May 24, 2018
    Inventors: William Jia, Xuexian Bu, I- Fang Lee
  • Semiconductor device and method of forming the same
    Patent number: 9972678
    Abstract: A method of forming a semiconductor device is provided including the following steps. A substrate having a first voltage area and a second voltage area is provided. A first oxide layer is formed in the first voltage area. The first oxide layer is removed to form a recess in the first voltage area. A shallow trench isolation (STI) structure is formed in the substrate, wherein a first portion of the STI structure is located in the first voltage area and a second portion of the STI structure is located in the second voltage area, a top surface of the STI structure is higher than the top surface of the substrate, and a bottom surface of the first portion of the STI structure in the first voltage area is lower than a bottom surface of the second portion of the STI structure in the second voltage area.
    Type: Grant
    Filed: October 6, 2016
    Date of Patent: May 15, 2018
    Assignee: United Microelectronics Corp.
    Inventors: Chang-Po Hsiung, Ping-Hung Chiang, Shih-Chieh Pu, Chia-Lin Wang, Nien-Chung Li, Wen-Fang Lee, Shih-Yin Hsiao, Chih-Chung Wang
  • Method of fabricating semiconductor device
    Patent number: 9972539
    Abstract: A semiconductor device and a method of fabricating the same, the semiconductor device includes a substrate, a first gate and a second gate. The first gate is disposed on the substrate and includes a first gate insulating layer, a polysilicon layer, a silicide layer and a protective layer stacked with each other on the substrate and a first spacer surrounds the first gate insulating layer, the polysilicon layer, the silicide layer and the protective layer. The second gate is disposed on the substrate and includes a second gate insulating layer, a work function metal layer and a conductive layer stacked with each other on the substrate, and a second spacer surrounds the second gate insulating layer, the work function metal layer and the conductive layer.
    Type: Grant
    Filed: March 30, 2017
    Date of Patent: May 15, 2018
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Shin-Hung Li, Kuan-Chuan Chen, Nien-Chung Li, Wen-Fang Lee, Chih-Chung Wang
  • SEMICONDUCTOR DEVICE AND METHOD OF FORMING THE SAME
    Publication number: 20180102408
    Abstract: A method of forming a semiconductor device is provided including the following steps. A substrate having a first voltage area and a second voltage area is provided. A first oxide layer is formed in the first voltage area. The first oxide layer is removed to form a recess in the first voltage area. A shallow trench isolation (STI) structure is formed in the substrate, wherein a first portion of the STI structure is located in the first voltage area and a second portion of the STI structure is located in the second voltage area, a top surface of the STI structure is higher than the top surface of the substrate, and a bottom surface of the first portion of the STI structure in the first voltage area is lower than a bottom surface of the second portion of the STI structure in the second voltage area.
    Type: Application
    Filed: October 6, 2016
    Publication date: April 12, 2018
    Applicant: United Microelectronics Corp.
    Inventors: Chang-Po Hsiung, Ping-Hung Chiang, Shih-Chieh Pu, Chia-Lin Wang, Nien-Chung Li, Wen-Fang Lee, Shih-Yin Hsiao, Chih-Chung Wang
  • HIGH-VOLTAGE METAL-OXIDE-SEMICONDUCTOR TRANSISTOR AND FABRICATION METHOD THEREOF
    Publication number: 20180097104
    Abstract: A high-voltage MOS transistor includes a semiconductor substrate, a gate oxide layer on the semiconductor substrate, a gate on the gate oxide layer, a spacer covering a sidewall of the gate, a source on one side of the gate, and a drain on the other side of the gate. The gate includes at least a first discrete segment and a second discrete segment. The first discrete segment is not in direct contact with the second discrete segment. The spacer fills into a gap between the first discrete segment and the second discrete segment.
    Type: Application
    Filed: November 22, 2017
    Publication date: April 5, 2018
    Inventors: Shih-Yin Hsiao, Kuan-Liang Liu, Ching-Chung Yang, Kai-Kuen Chang, Ping-Hung Chiang, Nien-Chung Li, Wen-Fang Lee, Chih-Chung Wang
  • Low drift ion selective electrode sensors
    Patent number: 9863908
    Abstract: An ion selective electrode sensor includes a housing containing an internal solution and enclosing a reference element containing a metal salt solution; open mesh fabric sieves traversing an opening in the housing; and at least one ion sensitive film layer on the mesh fabric sieves.
    Type: Grant
    Filed: April 10, 2014
    Date of Patent: January 9, 2018
    Assignee: BioChem Technology, Inc.
    Inventors: George Jaw Fang Lee, Sergey K. Maneshin, Steven Kestel
  • METHOD AND SYSTEM FOR SELECTING A COMMUNICATION INTERFACE
    Publication number: 20180007598
    Abstract: The disclosure is related to a method and a system for selecting a communication interface. The method is applicable to a local area network including multiple access points. A main access point is first selected. The main access point acquires every access point's information within a local area network. The information relates to the access points that are in an idle state or not performing a critical task. A target antenna can be selected for performing a specific function. For example, the target antenna can be used to scan for the channels specified in dynamic frequency selection. After that, the scan result may result in changing channels. Through the above mechanism, the resources in every AP within the LAN can be adequately used, and the performance of wireless communication can be effectively improved.
    Type: Application
    Filed: October 6, 2016
    Publication date: January 4, 2018
    Inventor: CHIH-FANG LEE
  • High-voltage metal-oxide-semiconductor transistor and fabrication method thereof
    Patent number: 9859417
    Abstract: A high-voltage MOS transistor includes a semiconductor substrate, a gate oxide layer on the semiconductor substrate, a gate on the gate oxide layer, a spacer covering a sidewall of the gate, a source on one side of the gate, and a drain on the other side of the gate. The gate includes at least a first discrete segment and a second discrete segment. The first discrete segment is not in direct contact with the second discrete segment. The spacer fills into a gap between the first discrete segment and the second discrete segment.
    Type: Grant
    Filed: June 24, 2016
    Date of Patent: January 2, 2018
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Shih-Yin Hsiao, Kuan-Liang Liu, Ching-Chung Yang, Kai-Kuen Chang, Ping-Hung Chiang, Nien-Chung Li, Wen-Fang Lee, Chih-Chung Wang
  • Semiconductor device and method for fabricating the same
    Patent number: 9852952
    Abstract: A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate having a logic region and high-voltage (HV) region; forming a first gate structure on the logic region and a second gate structure on the HV region; forming an interlayer dielectric (ILD) layer around the first gate structure and the second gate structure; forming a patterned hard mask on the HV region; and transforming the first gate structure into a metal gate.
    Type: Grant
    Filed: October 28, 2015
    Date of Patent: December 26, 2017
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Chih-Chung Wang, Shih-Yin Hsiao, Wen-Fang Lee, Nien-Chung Li, Shu-Wen Lin
  • HIGH-VOLTAGE METAL-OXIDE-SEMICONDUCTOR TRANSISTOR AND FABRICATION METHOD THEREOF
    Publication number: 20170345926
    Abstract: A high-voltage MOS transistor includes a semiconductor substrate, a gate oxide layer on the semiconductor substrate, a gate on the gate oxide layer, a spacer covering a sidewall of the gate, a source on one side of the gate, and a drain on the other side of the gate. The gate includes at least a first discrete segment and a second discrete segment. The first discrete segment is not in direct contact with the second discrete segment. The spacer fills into a gap between the first discrete segment and the second discrete segment.
    Type: Application
    Filed: June 24, 2016
    Publication date: November 30, 2017
    Inventors: Shih-Yin Hsiao, Kuan-Liang Liu, Ching-Chung Yang, Kai-Kuen Chang, Ping-Hung Chiang, Nien-Chung Li, Wen-Fang Lee, Chih-Chung Wang
  • NETWORK SYSTEM CAPABLE OF SWIFTLY ESTABLISHING WPS CONNECTION AND WPS CONNECTION METHOD THEREOF
    Publication number: 20170347383
    Abstract: A network system, which may include a target device, a plurality of network devices and a control device. The network devices may be connected to a network. The control device may be able to wirelessly communicate with the network devices via Wi-Fi. The control device may select one of the network devices as a designated device, and may control the designated device to execute the WPS connection process within a default time period before or after the target device executes the WPS connection process so as to establish the WPS connection between the target device and the designated device, whereby the target device may wirelessly communicate with the designated device via Wi-Fi.
    Type: Application
    Filed: January 10, 2017
    Publication date: November 30, 2017
    Inventors: FA-CHIANG LIU, CHIH-FANG LEE
  • METAL-OXIDE-SEMICONDUCTOR TRANSISTOR AND METHOD OF FORMING GATE LAYOUT
    Publication number: 20170330948
    Abstract: A method of forming a gate layout includes providing a gate layout design diagram comprising at least one gate pattern, disposing at least one insulating plug pattern in the gate pattern for producing a modified gate layout in a case where any one of a length and a width of the gate pattern is greater than or equal to a predetermined size, and outputting and manufacturing the modified gate layout onto a photomask. The predetermined size is determined by a process ability limit, and the process ability limit is a smallest gate size causing gate dishing when a chemical mechanical polishing process is performed to a gate.
    Type: Application
    Filed: August 4, 2017
    Publication date: November 16, 2017
    Inventors: Shih-Yin Hsiao, Ching-Chung Yang, Wen-Fang Lee, Nien-Chung Li, Chih-Chung Wang