Patents by Inventor An-Hao Lin

An-Hao Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240145455
    Abstract: An electronic package is provided, in which an electronic module including a first electronic element and a second electronic element is disposed on a carrier structure embedded with a third electronic element, and the third electronic element is a photonic chip electrically connected to the electronic module. Therefore, with this configuration, it is beneficial to reduce a layout area of the carrier structure to meet the requirement of miniaturization.
    Type: Application
    Filed: January 17, 2023
    Publication date: May 2, 2024
    Applicant: SILICONWARE PRECISION INDUSTRIES CO., LTD.
    Inventors: Meng-Jie LEE, Chih-Nan LIN, Ci-Hong YAN, Nai-Hao KAO
  • Publication number: 20240147506
    Abstract: Apparatus and methods are provided for dynamic sidelink (SL) resource allocation. In one novel aspect, one or more uplink (UL) resources are allocated for SL transceiving. In one embodiment, the UE establishes an SL connection with an SL peer UE, receives an allocation indication indicating one or more UL resources are available as shared SL resources for SL transceiving, wherein the allocation indication is originated from a gNB, and performs SL data transceiving with the SL peer UE using the one or more UL resources indicated in the allocation indication. In one embodiment, the UE receives the allocation indication through the Uu connection by unicast, multicast or broadcast. In one embodiment, the shared SL resources are indicated by RB ID or by SL grants. In one embodiment, conditions for using the shared SL resources are included in the allocation indication or are indicated in a separate RRC configuration.
    Type: Application
    Filed: October 12, 2023
    Publication date: May 2, 2024
    Inventors: Guan-Yu Lin, Chia-Hao Yu
  • Publication number: 20240145571
    Abstract: In some embodiments, the present disclosure relates to an integrated circuit (IC) in which a memory structure comprises an inhibition layer inserted between two ferroelectric layers to create a tetragonal-phase dominant ferroelectric structure. In some embodiments, the ferroelectric structure includes a first ferroelectric layer, a second ferroelectric layer overlying the first ferroelectric layer, and a first inhibition layer disposed between the first and second ferroelectric layers and bordering the second ferroelectric layer. The first inhibition layer is a different material than the first and second ferroelectric layers.
    Type: Application
    Filed: January 5, 2023
    Publication date: May 2, 2024
    Inventors: Po-Ting Lin, Yu-Ming Hsiang, Wei-Chih Wen, Yin-Hao Wu, Wu-Wei Tsai, Hai-Ching Chen, Yu-Ming Lin, Chung-Te Lin
  • Publication number: 20240145555
    Abstract: Semiconductor structures and processes are provided. A semiconductor structure of the present disclosure includes a first base portion and a second base portion extending lengthwise along a first direction, a first source/drain feature disposed over the first base portion, a second source/drain feature disposed over the second base portion, a center dielectric fin sandwiched between the first source/drain feature and the second source/drain feature along a second direction perpendicular to the first direction, and a source/drain contact disposed over the first source/drain feature, the second source/drain feature and the center dielectric fin. A portion of the source/drain contact extends between the first source/drain feature and the second source/drain feature along the second direction.
    Type: Application
    Filed: January 10, 2023
    Publication date: May 2, 2024
    Inventors: Ming-Heng Tsai, Chih-Hao Chang, Chun-Sheng Liang, Ta-Chun Lin
  • Publication number: 20240147825
    Abstract: Examples disclosed herein relate to device. The device includes a substrate, a plurality of adjacent pixel-defining layer (PDL structures disposed over the substrate, and a plurality of sub-pixels. The PDL structure have a top surface coupled to adjacent sidewalls of the PDL structure. The plurality of sub-pixels are defined by the PDL structures. Each sub-pixel includes an anode, an organic light emitting diode (OLED), a cathode, and an encapsulation layer. The organic light emitting diode (OLED) material disposed over the anode. The OLED material extends over the top surface of the PDL structure past the adjacent sidewalls. The cathode is disposed over the OLED material. The cathode extends over the top surface of the PDL structure past the adjacent sidewalls. The encapsulation layer is disposed over the cathode. The encapsulation layer has a first sidewall and a second sidewall.
    Type: Application
    Filed: October 26, 2022
    Publication date: May 2, 2024
    Inventors: Chung-chia CHEN, Yu-Hsin LIN, Ji Young CHOUNG, Jungmin LEE, Wen-Hao WU, Dieter HAAS
  • Publication number: 20240146864
    Abstract: A landmark identification and marking system for a panoramic image is provided. The system includes a storage device and a back-end processor. The storage device stores an initial panoramic image, attitude information, motion tracking information, and a landmark list. The back-end processor performs steps of: adjusting a visual angle of the initial panoramic image to a designated angle according to a difference value between the visual angle and the designated angle; providing the adjusted initial panoramic image to a front-end processor for calculating and generating a panoramic image integrated with landmark objects in the virtual space.
    Type: Application
    Filed: November 18, 2022
    Publication date: May 2, 2024
    Applicant: INSTITUTE FOR INFORMATION INDUSTRY
    Inventors: Jia-Hao WANG, Zhi-Ying CHEN, Hsun-Hui HUANG, Chien-Der LIN
  • Publication number: 20240145379
    Abstract: Methods and semiconductor devices are provided. A method includes determining a location of a polyimide opening (PIO) corresponding to an under-bump metallization (UBM) feature in a die. The die includes a substrate and an interconnect structure over the substrate. The method also includes determining a location of a stacked via structure in the interconnect structure based on the location of the PIO. The method further includes forming, in the interconnect structure, the stacked via structure comprising at most three stacked contact vias at the location of the PIO.
    Type: Application
    Filed: February 23, 2023
    Publication date: May 2, 2024
    Inventors: Yen-Kun Lai, Wei-Hsiang Tu, Ching-Ho Cheng, Cheng-Nan Lin, Chiang-Jui Chu, Chien Hao Hsu, Kuo-Chin Chang, Mirng-Ji Lii
  • Publication number: 20240146462
    Abstract: Apparatus and methods are provided for relay-assisted retransmission. In one novel aspect, the remote UE receives data transmission from the source entity through a direct link and retransmission from a relay UE. In one embodiment, the relay UE receives feedback indication from the remote UE, transmits the feedback to the source entity, and retransmits one or more TBs to the remote UE through a SL connection upon detecting one or assisted retransmission triggers. In one embodiment, the feedback is a joint HARQ, wherein a NACK is sent when both the relay UE and remote UE failed, and an ACK is sent when at least one of the relay UE and the remote UE succeeds. In one embodiment, the relay UE retransmits one or more successfully received TBs to the remote UE upon receiving a failure indication from the remote UE or receiving retransmission indication from the source entity.
    Type: Application
    Filed: October 12, 2023
    Publication date: May 2, 2024
    Inventors: Guan-Yu Lin, Chia-Hao Yu
  • Publication number: 20240138326
    Abstract: A control method for preparing crop nutrient solution, applied in a regulating device, obtains growth data of crops, and determines a growth state of the crops according to the growth data of the crops. The proportion of the nutrient solution required by the crops is determined according to the growth states of the crops, and the culture solution is adjusted according to the proportion of the nutrient solution. After a preset time period, updated growth state of the crops is determined. When the culture solution does not meet the proportion of the nutrient solution corresponding to the updated growth state, the culture solution is adjusted again until the culture solution meet the proportion of the nutrient solution corresponding to the growth state of the crops.
    Type: Application
    Filed: March 28, 2023
    Publication date: May 2, 2024
    Inventors: YU-SHAN LIN, CHIEN-HAO SU, KAI-SIANG YOU, YAO-WEN TUNG
  • Publication number: 20240142664
    Abstract: Two types of blue light blocking contact lenses are provided and are formed by curing different compositions. The first composition includes a blue light blocking component formed by mixing or reacting a first hydrophilic monomer and a yellow dye, a first colored dye component formed by mixing or reacting a second hydrophilic monomer and a first colored dye, at least one third hydrophilic monomer, a crosslinker, and an initiator. The first colored dye includes a green dye, a cyan dye, a blue dye, an orange dye, a red dye, a black dye, or combinations thereof. The second composition includes a blue light blocking component, at least one hydrophilic monomer, a crosslinker, and an initiator. The blue light blocking component is formed by mixing or reacting glycerol monomethacrylate and a yellow dye. Further, methods for preparing the above contact lenses are provided.
    Type: Application
    Filed: February 12, 2023
    Publication date: May 2, 2024
    Inventors: Han-Yi CHANG, Chun-Han CHEN, Tsung-Kao HSU, Wei-che WANG, Yu-Hung LIN, Wan-Ying GAO, Li-Hao LIU
  • Publication number: 20240145498
    Abstract: Some embodiments relate to an integrated chip including a substrate having a first side and a second side opposite the first side. The integrated chip further includes a first photodetector positioned in a first pixel region within the substrate. A floating diffusion region with a first doping concentration of a first polarity is positioned on the first side of the substrate in the first pixel region. A first body contact region with a second doping concentration of a second polarity different from the first polarity is positioned on the second side of the substrate in the first pixel region.
    Type: Application
    Filed: January 4, 2023
    Publication date: May 2, 2024
    Inventors: Hao-Lin Yang, Fu-Sheng Kuo, Ching-Chun Wang, Hsiao-Hui Tseng, Tzu-Jui Wang, Chen-Jong Wang, Dun-Nian Yaung
  • Patent number: 11972363
    Abstract: Methods, systems, and apparatus, including computer programs encoded on a computer storage medium, for obtaining a plurality of model representations of predictive models, each model representation associated with a respective user and expresses a respective predictive model, and selecting a model implementation for each of the model representations based on one or more system usage properties associated with the user associated with the corresponding model representation.
    Type: Grant
    Filed: May 22, 2020
    Date of Patent: April 30, 2024
    Assignee: Google LLC
    Inventors: Wei-Hao Lin, Travis H. K. Green, Robert Kaplow, Gang Fu, Gideon S. Mann
  • Patent number: 11973010
    Abstract: A chip packaging method includes: providing a wafer, on which multiple bumps are formed; cutting the wafer into multiple chip units, wherein multiple vertical heat conduction elements are formed on the wafer or the chip units; disposing the chip units on a base material; and providing a package material to encapsulate lateral sides and a bottom surface of each of the chip units, to form a chip package unit, wherein the bottom surface of the chip unit faces the base material; wherein, in the chip package unit, the bumps on the chip units abut against the base material, and wherein the vertical heat conduction elements directly connect to the base material, or the base material includes multiple through-holes and the vertical heat conduction elements pass through the multiple through-holes in the base material.
    Type: Grant
    Filed: September 30, 2021
    Date of Patent: April 30, 2024
    Assignee: RICHTEK TECHNOLOGY CORPORATION
    Inventors: Hao-Lin Yen, Heng-Chi Huang, Yong-Zhong Hu
  • Patent number: 11972557
    Abstract: Provided are a vibration object monitoring method and apparatus, a computer device, and a storage medium. The method includes: in response to detecting that a vibration object exists in a monitoring video picture for a target monitoring region, a vibration object region in the monitoring video picture is determined, where the vibration object region is a region where the vibration object is located in the monitoring video picture; displacement information of a key point of the vibration object in the vibration object region is recorded; vibration information of the vibration object in the monitoring video picture is determined based on the displacement information; and a vibration object monitoring result for the target monitoring region is generated according to the vibration information. The abnormal vibration monitoring can be performed on the vibration object in the target monitoring region in time according to this method.
    Type: Grant
    Filed: March 8, 2021
    Date of Patent: April 30, 2024
    Assignee: CSG POWER GENERATION CO., LTD.
    Inventors: Yumin Peng, Zhiqiang Wang, Hao Zhang, Hengjun Chen, Xun Hu, Tuixiang Feng, Liqun Sun, Man Chen, Yong Lu, Tao Liu, Kai Lin, Yulin Han
  • Patent number: 11973039
    Abstract: A semiconductor device package includes a semiconductor die, a first conductive element, a second conductive element, a metal layer, and a first redistribution layer (RDL). The semiconductor die includes a first surface and a second surface opposite to the first surface. The first conductive element is disposed on the second surface of the semiconductor die. The second conductive element is disposed next to the semiconductor die. The metal layer is disposed on the second conductive element and electrically connected to the second conductive element. The first RDL is disposed on the metal layer and electrically connected to the metal layer.
    Type: Grant
    Filed: June 1, 2021
    Date of Patent: April 30, 2024
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Chia-Hao Sung, Hsuan-Yu Chen, Yu-Kai Lin
  • Publication number: 20240136428
    Abstract: Improved inner spacers for semiconductor devices and methods of forming the same are disclosed.
    Type: Application
    Filed: January 2, 2024
    Publication date: April 25, 2024
    Inventors: Wen-Kai Lin, Che-Hao Chang, Chi On Chui, Yung-Cheng Lu
  • Publication number: 20240136366
    Abstract: A display panel and a display device are provided. The display panel includes a display region and a non-display region. The non-display region includes a demultiplexing circuit, a fanout wire, and a clock signal line. An input terminal of the demultiplexing circuit is electrically connected to the fanout wire, an output terminal of the demultiplexing circuit is electrically connected to a data line in the display region, and a control terminal of the demultiplexing circuit is electrically connected to the clock signal line. The display panel further includes an isolation signal line including an isolation portion, and an orthographic projection of the isolation portion on a plane where a substrate is located is between an orthographic projection of the clock signal line on the plane where the substrate is located and an orthographic projection of the fanout wire on the plane where the substrate is located.
    Type: Application
    Filed: January 4, 2024
    Publication date: April 25, 2024
    Applicant: Xiamen Tianma Microelectronics Co., Ltd.
    Inventors: Guangdeng YANG, Yiqiang LIN, Dongxu QIU, Hao WU, Poping SHEN
  • Publication number: 20240137483
    Abstract: An exemplary embodiment of the invention provides an image processing method for a virtual reality display system. The method includes: enabling a first shared buffer and a second shared buffer; performing an image capturing operation to obtain a first image from a virtual reality scene; storing the first image to the first shared buffer; in response to that the storing of the first image is finished, reading the first image from the first shared buffer; performing a depth estimation operation on the first image to obtain depth information corresponding to the first image; storing the depth information to the second shared buffer; in response to that the storing of the depth information is finished, reading the depth information from the second shared buffer; performing an image generation operation according to the depth information to generate a pair of second images corresponding to the virtual reality scene; and outputting the pair of second images by a display of the virtual reality display system.
    Type: Application
    Filed: October 18, 2022
    Publication date: April 25, 2024
    Applicant: Acer Incorporated
    Inventors: Sergio Cantero Clares, Wen-Cheng Hsu, Shih-Hao Lin, Chih-Haw Tan
  • Publication number: 20240136298
    Abstract: A method includes dispensing sacrificial region over a carrier, and forming a metal post over the carrier. The metal post overlaps at least a portion of the sacrificial region. The method further includes encapsulating the metal post and the sacrificial region in an encapsulating material, demounting the metal post, the sacrificial region, and the encapsulating material from the carrier, and removing at least a portion of the sacrificial region to form a recess extending from a surface level of the encapsulating material into the encapsulating material.
    Type: Application
    Filed: January 2, 2024
    Publication date: April 25, 2024
    Inventors: Jing-Cheng Lin, Chen-Hua Yu, Po-Hao Tsai
  • Publication number: 20240136291
    Abstract: Semiconductor devices and methods of forming the same are provided. In some embodiments, a method includes receiving a workpiece having a redistribution layer disposed over and electrically coupled to an interconnect structure. In some embodiments, the method further includes patterning the redistribution layer to form a recess between and separating a first conductive feature and a second conductive feature of the redistribution layer, where corners of the first conductive feature and the second conductive feature are defined adjacent to and on either side of the recess. The method further includes depositing a first dielectric layer over the first conductive feature, the second conductive feature, and within the recess. The method further includes depositing a nitride layer over the first dielectric layer. In some examples, the method further includes removing portions of the nitride layer disposed over the corners of the first conductive feature and the second conductive feature.
    Type: Application
    Filed: January 12, 2023
    Publication date: April 25, 2024
    Inventors: Hsiang-Ku SHEN, Chen-Chiu HUANG, Chia-Nan LIN, Man-Yun WU, Wen-Tzu CHEN, Sean YANG, Dian-Hao CHEN, Chi-Hao CHANG, Ching-Wei LIN, Wen-Ling CHANG