Patents by Inventor An Hsieh

An Hsieh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11705918
    Abstract: An incremental analog-to-digital converter including a first-stage non-delay memorization element and other elements is disclosed. An ending time point of a second reset signal received by the first-stage non-delay memorization element is later than an ending time point of a first reset signal received by the other elements by at least one clock cycle, a reset duration of the first-stage non-delay memorization element is longer than a reset duration of the other element, so that the first-stage non-delay memorization element can be prevented from occurring overshoot or spike on an output thereof, and the incremental analog-to-digital converter can maintain a good signal-to-noise and distortion ratio under the condition that the internal elements has low swing limits.
    Type: Grant
    Filed: February 25, 2022
    Date of Patent: July 18, 2023
    Assignee: NUVOTON TECHNOLOGY CORPORATION
    Inventor: Chung Ming Hsieh
  • Patent number: 11703964
    Abstract: The present disclosure provides a switch, which includes a first input port, a second input port, an output port and a control circuit. The output port outputs image data received by the first input port. The control circuit receives a first electrical characteristic and a second electrical characteristic from the first input port and the second input port respectively, and changes a third electrical characteristic of the output port when the second electrical characteristic is different from the first electrical characteristic, and then the output port outputs image data received by the second input port.
    Type: Grant
    Filed: June 17, 2021
    Date of Patent: July 18, 2023
    Assignee: ATEN INTERNATIONAL CO., LTD.
    Inventors: Yan-Chan Huang, Yen-Yang Hsieh
  • Patent number: 11703769
    Abstract: A light source for EUV radiation is provided. The light source includes a target droplet generator, a laser generator, and a controller. The target droplet generator is configured to provide target droplets to a source vessel. The laser generator is configured to provide a plurality of first laser pulses according to a control signal to irradiate the target droplets in the source vessel to generate plasma as the EUV radiation. The controller is configured to provide the control signal according to the temperature of the source vessel and droplet positions of the target droplets. When the temperature of the source vessel exceeds a temperature threshold value and a standard deviation of the droplet positions of the target droplets exceeds a first standard deviation threshold value, the controller is configured to provide the control signal to the laser generator, so as to stop providing the first laser pulses.
    Type: Grant
    Filed: May 16, 2022
    Date of Patent: July 18, 2023
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chi Yang, Ssu-Yu Chen, Shang-Chieh Chien, Chieh Hsieh, Tzung-Chi Fu, Bo-Tsun Liu, Li-Jui Chen, Po-Chung Cheng
  • Patent number: 11701399
    Abstract: A composition for modulating intestinal permeability and/or treating and/or preventing leaky gut related diseases including a Chinese herbal compound material or a Chinese herbal compound extract is provided. The Chinese herbal compound material includes Ganoderma, red jujube, longan and lotus seed. Moreover, the Chinese herbal compound extract includes a Ganoderma extract, a red jujube extract, a longan extract and a lotus seed extract.
    Type: Grant
    Filed: December 30, 2020
    Date of Patent: July 18, 2023
    Assignee: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
    Inventors: I-Hong Pan, Kuei-Chang Li, Zong-Keng Kuo, Chu-Hsun Lu, Yen-Wu Hsieh, Shu-Fang Wen
  • Publication number: 20230221285
    Abstract: Systems and techniques for measuring process characteristics including electrolyte distribution in a battery cell. A non-destructive method for analyzing a battery cell includes determining acoustic features at two or more locations of the battery cell, the acoustic features based on one or more of acoustic signals travelling through at least one or more portions of the battery cell during one or more points in time or responses to the acoustic signals obtained during one or more points in time, wherein the one or more points in time correspond to one or more stages of electrolyte distribution in the battery cell. One or more characteristics of the battery cell are determined based on the acoustic features at the two or more locations of the battery cell.
    Type: Application
    Filed: March 6, 2023
    Publication date: July 13, 2023
    Inventors: Shan Dou, Andrew G. Hsieh, Shaurjo Biswas, Barry J. Van Tassell, Elizabeth M. Lee, Dennis Yu, Jason Y. Yu
  • Publication number: 20230222956
    Abstract: An electronic device includes an array substrate. The array substrate includes first to third gate lines, a first to third pixel units, and a gate driving circuit. The third gate line is disposed between the first and second gate lines. The first pixel unit is electrically connected to the first gate line and the data line. The second pixel unit is electrically connected to the second gate line and the data line. The third pixel unit is electrically connected to the third gate line and the data line. The gate driving circuit is electrically connected to the first to third gate lines. The gate driving circuit provides a first gate driving signal to the first pixel unit, a second gate driving signal to the second pixel unit, and a third gate driving signal to the third pixel unit in a time sequence.
    Type: Application
    Filed: December 7, 2022
    Publication date: July 13, 2023
    Applicant: Innolux Corporation
    Inventors: Chan-Feng Chiu, Ming-Feng Hsieh, Li-Jin Wang, Meng-Chang Tsai
  • Publication number: 20230223482
    Abstract: An optical semiconductor device with cascade vias is disclosed. The semiconductor device a logic die having a core circuit area and a logic peripheral circuit area; a memory die positioned on the logic die and having a memory cell area and a memory peripheral area; a first inter-die via positioned in the memory peripheral area; a landing pad positioned on the first inter-die via; and a sensor die positioned on the memory die and including a sensor pixel area and a sensor peripheral area, a first intra-die via positioned in the sensor peripheral area. The first inter-die via and the first intra-die via are electrically coupled through the landing pad in a cascade manner.
    Type: Application
    Filed: January 11, 2022
    Publication date: July 13, 2023
    Inventor: MING-HUNG HSIEH
  • Publication number: 20230218623
    Abstract: A salt of a neuroceutical and of an acid, wherein the neuroceutical is a substituted benzodiazepine, a substituted benzothiazepine, a substituted pyridopyrimidines or a substituted amino-cyclohexaneacetic acid; and the acid is benzoic acid, nicotinic acid, pantothenic acid and tannic acid. The molar ratio of the neuroceutical and the acid in the salt ranges from about 6:1 to about 1:5. Also disclosed herein are compositions comprising the neuroceutical salt and therapeutic uses thereof for treating a central nervous system (CNS) disorder or a metabolic disorder associated with the CNS disorder.
    Type: Application
    Filed: May 5, 2021
    Publication date: July 13, 2023
    Inventors: Guochuan Emil Tsai, Ching-Cheng Wang, Tien-Lan Hsieh, Yi-Feng Huang, Hsin-Hsin Yang, Ming-Hong Chien, Han-Yi Hsieh, Wei-Hua Chang
  • Publication number: 20230225087
    Abstract: A power module and a power device are provided. The power device includes two screws, a heat dissipation components and a power module. The power module includes a substrate, a package body and two fixing structures. Each fixing structure includes a first through hole, two second through holes, an annular structure and two sinking structures. When the power module is fixed to the heat dissipation component, each sinking structure is bent toward the heat dissipation component, and each annular structure is fixed to the flat surface of the heat dissipation component by the screws. The heat dissipation surface of the substrate can be flatly attached to the flat surface of the heat dissipation component through the two fixed structures, so that the heat energy generated during the operation of the power module can be transferred out through the heat dissipation component.
    Type: Application
    Filed: September 9, 2022
    Publication date: July 13, 2023
    Inventors: Chung-Ming LENG, Chih-Cheng HSIEH, Wei-Lun Wang
  • Publication number: 20230223392
    Abstract: An integrated circuit includes a first gate electrode structure extending in a first direction. The integrated circuit includes a second gate electrode structure extending in the first direction and separated in a second direction from the first gate electrode structure. The integrated circuit includes a conductive feature. The conductive feature includes a first section electrically connected to the second portion, a second section electrically connected to the second gate structure, and a third section electrically connecting the first section and the second section, wherein the third section extends in a third direction angled with respect to both the first direction and the second direction.
    Type: Application
    Filed: March 15, 2023
    Publication date: July 13, 2023
    Inventors: Tung-Heng HSIEH, Ting-Wei CHIANG, Chung-Te LIN, Hui-Zhong ZHUANG, Li-Chun TIEN, Sheng-Hsiung WANG
  • Publication number: 20230221191
    Abstract: The present disclosure provides a temperature sensing device and a calibration method thereof. The temperature sensing device includes a current generation circuit, an analog-to-digital conversion (ADC) circuit and a processing circuit. The calibration method includes: by the current generation circuit, generating a temperature dependent current according to a temperature of a tested object, wherein the temperature dependent current is dependent on a reference current passing through an adjustable resistor of the current generation circuit; by the ADC circuit, performing an analog-to-digital conversion according to the temperature dependent current to generate a sensing value; by the processing circuit, comparing the sensing value with an ideal value; and by the processing circuit, adjusting a resistance value of the adjustable resistor according to a comparison result of the sensing value and the ideal value, so that the sensing value equals the ideal value.
    Type: Application
    Filed: December 6, 2022
    Publication date: July 13, 2023
    Inventors: Wen-Pin HSIEH, Yu-Chieh HUNG, Chih-Wen YANG
  • Publication number: 20230222625
    Abstract: The embodiments of the disclosure provide a method for adjusting a virtual object, a host, and a computer readable storage medium. The method includes: obtaining a first field of view (FOV) of a virtual world; obtaining a second FOV of a camera, wherein a first physical object locates within the second FOV of the camera; determining a FOV ratio based on the first FOV and the second FOV; determining a first position of a first virtual object in the virtual world relative to a reference object in the virtual world, wherein the first virtual object corresponds to the first physical object; determining a second position of the first virtual object in the virtual world based on the first position and the FOV ratio; and showing the first virtual object at the second position in the virtual world.
    Type: Application
    Filed: May 4, 2022
    Publication date: July 13, 2023
    Applicant: HTC Corporation
    Inventors: SyuanYu Hsieh, Sheng-Kun Huang
  • Publication number: 20230225050
    Abstract: A circuit board structure includes a circuit substrate, a first circuit layer, and a second circuit layer. The circuit substrate has a surface and includes at least one conductive structure and at least one patterned circuit layer. The conductive structure is electrically connected to the patterned circuit layer, and an upper surface of the conductive structure is aligned with the surface. The first circuit layer is directly disposed on the surface of the circuit substrate and electrically connected to the conductive structure. A line width of the first circuit layer is less than or equal to ¼ of a line width of the patterned circuit layer. The second circuit layer is directly disposed on the first circuit layer and electrically connected to the first circuit layer.
    Type: Application
    Filed: August 30, 2022
    Publication date: July 13, 2023
    Applicant: Unimicron Technology Corp.
    Inventors: Kuang-Ching Fan, Chih-Peng Hsieh, Cheng-Hsiung Wang
  • Publication number: 20230223357
    Abstract: A method of manufacturing a semiconductor package includes depositing a first dielectric layer over a carrier substrate. A first metallization pattern is formed over the first dielectric layer. The first metallization pattern has a first opening exposing the first dielectric layer. A second dielectric layer is deposited over the first metallization pattern, forming a dielectric slot through the first metallization pattern by filling the first opening. A second metallization pattern and a third dielectric layer are formed over the second dielectric layer. A through via is formed over the third dielectric layer, so that the dielectric slot is laterally under the through via.
    Type: Application
    Filed: May 24, 2022
    Publication date: July 13, 2023
    Inventors: Yi-Che Chiang, Chien-Hsun Chen, Tuan-Yu Hung, Hsin-Yu Pan, Wei-Kang Hsieh, Tsung-Hsien Chiang, Chao-Hsien Huang, Tzu-Sung Huang, Ming Hung Tseng, Wei-Chih Chen, Ban-Li Wu, Hao-Yi Tsai, Yu-Hsiang Hu, Chung-Shi Liu
  • Publication number: 20230223385
    Abstract: The present disclosure provides an electronic device including a driving circuit substrate, a plurality of chips, and a passivation layer. The driving circuit substrate includes a plurality of active elements. The chips are disposed on the driving circuit substrate and electrically connected to the driving circuit substrate. The passivation layer covers the plurality of chips and the driving circuit substrate. The passivation layer has a first part on one of the plurality of chips and a second part on a part of the driving circuit substrate, the second part is not overlapped with the plurality of chips, and a first thickness of the first part is less than a second thickness of the second part. The first space between adjacent two of the plurality of chips is different from a second space between another adjacent two of the plurality of chips.
    Type: Application
    Filed: March 17, 2023
    Publication date: July 13, 2023
    Applicant: InnoLux Corporation
    Inventors: Shu-Ming Kuo, Tsau-Hua Hsieh, Shun-Yuan Hu
  • Publication number: 20230221522
    Abstract: An optical lens assembly, including a first lens element, a second lens element, a third lens element, a fourth lens element, and a fifth lens element sequentially along an optical axis from a first side to a second side, is provided. The optical lens assembly satisfies the conditional expression of D34/D12?2.600. Furthermore, other optical lens assemblies are also provided.
    Type: Application
    Filed: January 16, 2023
    Publication date: July 13, 2023
    Applicant: GENIUS ELECTRONIC OPTICAL (XIAMEN) CO., LTD.
    Inventors: Huabin Liao, Qingzhi Zhu, Jiayuan Zhang, Hung-Chien Hsieh
  • Publication number: 20230223382
    Abstract: A semiconductor package includes a lower semiconductor device, a plurality of conductive pillars, an upper semiconductor device, an encapsulating material, and a redistribution structure. The plurality of conductive pillars are disposed on the lower semiconductor device along a direction parallel to a side of the lower semiconductor device. The upper semiconductor device is disposed on the lower semiconductor device and reveals a portion of the lower semiconductor device where the plurality of conductive pillars are disposed, wherein the plurality of conductive pillars disposed by the same side of the upper semiconductor device and the upper semiconductor device comprises a cantilever part cantilevered over the at least one lower semiconductor device. The encapsulating material encapsulates the lower semiconductor device, the plurality of conductive pillars, and the upper semiconductor device. The redistribution structure is disposed over the upper semiconductor device and the encapsulating material.
    Type: Application
    Filed: March 16, 2023
    Publication date: July 13, 2023
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Wei-Kang Hsieh, Hung-Yi Kuo, Hao-Yi Tsai, Kuo-Lung Pan, Ting Hao Kuo, Yu-Chia Lai, Mao-Yen Chang, Po-Yuan Teng, Shu-Rong Chun
  • Publication number: 20230223765
    Abstract: The present invention discloses a method and system for charging rechargeable battery cells in series. When the voltage of a specific battery cell is too high, discharge the specific battery cell, and at the same time let other battery cells with lower voltage continue to charge, so that each battery cell in series can be charged to almost the same level. This invention designs in a “Total voltage follow-up charging method”, a Battery Manage System (BMS) detects total voltage of the series-connected battery in real-time and modifies an “equalizing trigger voltage”, as the total voltage drifts the equaling function still works well.
    Type: Application
    Filed: January 13, 2022
    Publication date: July 13, 2023
    Inventor: Fang-Chi HSIEH
  • Publication number: 20230222980
    Abstract: In examples, an electronic device comprises a camera and a display having a transparent area aligned with the camera. The display comprises a first line corresponding to a pixel row or column of the display, the first line extending from a first end of the display to the transparent area. The display comprises a second line corresponding to the pixel row or column and extending from a second end of the display to the transparent area, the first and second lines separated by a gap. The electronic device includes a controller coupled to the display, the controller to drive the first and second lines consecutively.
    Type: Application
    Filed: May 15, 2020
    Publication date: July 13, 2023
    Applicant: Hewlett-Packard Development Company, L.P.
    Inventors: Hsing-Hung Hsieh, Super Liao, Kuan-Ting Wu
  • Publication number: 20230223215
    Abstract: A keyboard device includes a substrate, a keycap, and a link member. The keycap is disposed on the substrate and provided with a limiting member including a top wall, a bottom wall, and a slide groove. In the slide groove, the top wall has a first guide bevel and the bottom wall has a second guide bevel. The link member is disposed between the substrate and the keycap and includes a slide connection portion and a pivot connection portion. The slide connection portion is slidably disposed in the slide groove, and the pivot connection portion is pivotally connected to the substrate. When the keycap is pressed to move downwardly toward the substrate, the pivot connection portion of the link member is rotated with respect to the substrate, and the slide connection portion slides along the first guide bevel and the second guide bevel.
    Type: Application
    Filed: August 24, 2022
    Publication date: July 13, 2023
    Inventors: Chun-Chieh Chan, Chao-Chin Hsieh