Abstract: A knowledge graph construction system and method are disclosed. The system generates a recommended subject entity, at least one recommended object entity, and at least one recommended relation for a piece of text data according to the text data and a plurality of triples. The system displays the recommended object entity and the recommended relation at a current paragraph of the text data according to the recommended subject entity for user to select. The system receives a confirmed message related to the recommended subject entity, a recommended object entity selected by user from the at least one recommended object entity, and a recommended relation selected by user from the at least one recommended relation. The system adds the recommended subject entity and the selected recommended object entity and recommended relation to the triples, and constructs a current knowledge graph by using the triples according to the confirmed message.

Abstract: A ternary content addressable memory and a memory cell thereof are provided. The ternary content addressable memory cell includes a first transistor and a second transistor. The first transistor has a gate to receive a selection signal. A first end of the first transistor is coupled to a match line. A second end of the first transistor is coupled to a source line. The second transistor has a gate to receive an inverted selection signal. A first end of the second transistor is coupled to the match line. A second end of the second transistor is coupled to the source line. The first and second transistors have charge storage structures.

Abstract: A mouse device includes a housing, a switch, a button, and a biasing member. The housing has an accommodating space therein. The switch is disposed in the accommodating space. The button covers the housing and includes a pivotal portion and a trigger portion. The pivotal portion is pivotally connected to the housing. The trigger portion extends into the accommodating space. The biasing member is located between the pivotal portion and the trigger portion and forwardly exerts force to the button in a forward-backward axial direction of the mouse device.

Abstract: A semiconductor structure and a manufacturing method for the same. The semiconductor structure includes a plug element and a via element. The plug element includes a tungsten plug. The plug element has a plug size in a lateral direction. The via element is electrically connected on the plug element. The via element is non-symmetrical with respect a center line of the plug element extending along a longitudinal direction. The via element has a via size in the lateral direction. The plug size is bigger than the via size.

Abstract: A ternary content addressable memory and a memory cell thereof are provided. The ternary content addressable memory cell includes a first transistor and a second transistor. The first transistor has a gate to receive a selection signal. A first end of the first transistor is coupled to a match line. A second end of the first transistor is coupled to a source line. The second transistor has a gate to receive an inverted selection signal. A first end of the second transistor is coupled to the match line. A second end of the second transistor is coupled to the source line. The first and second transistors have charge storage structures.

Abstract: A TCAM comprises a plurality of first search lines, a plurality of second search lines, a plurality of memory cell strings and one or more current sensing units. The memory cell strings comprise a plurality of memory cells. Each of the memory cells is coupled to one of the first search lines and one of the second search lines. The current sensing units, coupled to the memory cell strings. In a search operation, a determination that whether any of the data stored in the memory cell strings matches a data string to be searched is made according to whether the one or more current sensing units detect current from the memory cell strings, or according to the magnitude of the current flowing out from the memory cell strings detected by the one or more current sensing units.

Abstract: A memory cell includes: a transistor having a control terminal coupled to a first node; a first terminal coupled to a first signal line; and a second terminal coupled to a second signal line; a first resistance element, having a first terminal coupled to the first node and a second terminal coupled to a second node; and a second resistance element, having a first terminal coupled to the first node and a second terminal coupled to a third node.

Abstract: Machine learning of model parameters for a neural network using a computing system is provided, that produces error-aware model parameters. An iterative process to converge on trained model parameters to be applied in the inference engine, includes applying a sequence of input training data sets to a neural network to produce inference results for the sequence using a set of model parameters in the neural network combined with factors based on a model of non-ideal characteristics of target memory to provide a training set of model parameters. An inference engine using the target memory technology to store the model parameters can have more stable results across a large number of engines.

Abstract: An in-memory computing device includes a plurality of synaptic layers including a first type of synaptic layer and a second type of synaptic layer. The first type of synaptic layer comprises memory cells of a first type of memory cell and the second type of synaptic layer comprises memory cells of a second type, the first type of memory cell being different than the second type of memory cell. The first and second types of memory cells can be different types of memories, have different structures, different memory materials, and/or different read/write algorithms, any one of which can result in variations in the stability or accuracy of the data stored in the memory cells.

Abstract: A semiconductor structure and a manufacturing method for the same. The semiconductor structure includes a plug element and a via element. The plug element includes a tungsten plug. The plug element has a plug size in a lateral direction. The via element is electrically connected on the plug element. The via element is non-symmetrical with respect a center line of the plug element extending along a longitudinal direction. The via element has a via size in the lateral direction. The plug size is bigger than the via size.

Abstract: A mouse device includes a housing, a switch, a button, and a biasing member. The housing has an accommodating space therein. The switch is disposed in the accommodating space. The button covers the housing and includes a pivotal portion and a trigger portion. The pivotal portion is pivotally connected to the housing. The trigger portion extends into the accommodating space. The biasing member is located between the pivotal portion and the trigger portion and downwardly exerts a force to the button in an upward-downward axial direction of the mouse device.

Abstract: A surgical system includes: (1) an imaging device configured to acquire imaging data of a surgical site; (2) a surgical manipulator configured to hold a surgical tool; and (3) a controller connected to the imaging device and the surgical manipulator, wherein the controller is configured to receive the imaging data from the imaging device and derive, from the imaging data, an insertion trajectory for the surgical tool through an incision at the surgical site.

Abstract: A random number generator, a random number generating circuit, and a random number generating method are provided. The random number generating circuit includes the random number generator and executes the random number generating method. The random number generator includes a shift register having N storage elements and a combinational logic circuit. The N storage elements receive a random seed in a static state and repetitively perform a bit shift operation in a plurality of clock cycles. The combinational logic circuit generates an output sequence based on the random seed and a random bitstream received from an external source.

Abstract: A method for forming a memory device includes the steps of providing a substrate, forming an isolation structure in the substrate to define a plurality of active regions in the substrate, the active regions respectively comprising two terminal portions and a central portion between the terminal portions, forming a plurality of island features on the substrate, wherein each of the island features covers two of the terminals portions respectively belonging to two of the active regions, performing a first etching process, using the island features as an etching mask to etch the substrate to define a plurality of island structures and a first recessed region surrounding the island structures on the substrate, and removing the island features to expose the island structures.

Abstract: A mouse device includes a housing, a switch, a button, and a biasing member. The housing has an accommodating space therein. The switch is disposed in the accommodating space. The button covers the housing and includes a pivotal portion and a trigger portion. The pivotal portion is pivotally connected to the housing. The trigger portion extends into the accommodating space. The biasing member is located between the pivotal portion and the trigger portion and forwardly exerts force to the button in a forward-backward axial direction of the mouse device.

Abstract: A mouse device includes a housing, a switch, a button, and a biasing member. The housing has an accommodating space therein. The switch is disposed in the accommodating space. The button covers the housing and includes a pivotal portion and a trigger portion. The pivotal portion is pivotally connected to the housing. The trigger portion extends into the accommodating space. The biasing member is located between the pivotal portion and the trigger portion and downwardly exerts a force to the button in an upward-downward axial direction of the mouse device.

Abstract: A method for forming a memory device is disclosed, including providing a substrate, forming an isolation structure and plural active regions in the substrate, forming a plurality of island features on the substrate respectively covering two of the terminal portions of the active regions, using the island features as an etching mask to etch the substrate to perform a first etching process to define a first recessed region and plural island structures on the substrate. The island structures respectively comprise the two terminal portions of the active regions and the first recessed region comprises the central portions of the active regions.

Abstract: A method for forming patterns is provided in the present invention. The process includes the steps of using a first mask to perform a first exposure process to a photoresist, using a second mask to perform a second exposure process to the photoresist, wherein the corners of the second opening patterns in the second mask and the corners of the first opening patterns in the first mask overlap each other, and performing a development process to remove the unexposed portions of the photoresist in the two exposure processes to form staggered hole patterns therein.

Abstract: A semiconductor device for performing a sum-of-product computation and an operating method thereof are provided. The semiconductor device includes an inputting circuit, a scaling circuit, a computing memory and an outputting circuit. The inputting circuit is used for receiving a plurality of inputting signals. The inputting signals are voltages or currents. The scaling circuit is connected to the inputting circuit for transforming the inputting signals to be a plurality of compensated signals respectively. The compensated signals are voltages or currents. The computing memory is connected to the scaling circuit. The computing memory includes a plurality of computing cells and the compensated signals are applied to the computing cells respectively. The outputting circuit is connected to the computing memory for reading an outputting signals of the computing cells. The outputting signal is voltage or current.