Patents by Inventor AN-HSIUNG CHANG
AN-HSIUNG CHANG has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240192538Abstract: A display apparatus having a privacy mode and a sharing mode is provided. The display apparatus includes a display panel, a privacy liquid crystal module, and a touch sensing module. The touch sensing module is disposed on a side of the privacy liquid crystal module and is configured to generate a touch signal. When the display apparatus is in the privacy mode, the privacy liquid crystal module is applied with a first voltage. When the display apparatus is in the sharing mode and the touch sensing module generates the touch signal, the privacy liquid crystal module is applied with a second voltage for a predetermined time. After maintaining for the predetermined time, a third voltage is applied to the privacy liquid crystal module. The display apparatus can effectively reduce a smear phenomenon caused by the display apparatus being touched in a sharing mode.Type: ApplicationFiled: December 3, 2023Publication date: June 13, 2024Applicant: Coretronic CorporationInventors: Chih-Hsuan Kuo, Ming-Hsiung Fan, Yi-Cheng Lin, Chin-Lung Chen, Cheng-Wei Zhu, Chin-Yuan Chang
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Publication number: 20240193473Abstract: A machine learning system and method for optical critical dimension measurement. From a training set of spectra and references, features are extracted and subjected to regression analysis to generate predictor variables. Using feature functions, inverse feature functions, a machine-learning predictor component and masks, a machine-learning optical critical dimension explainer is generated. A wafer is analyzed by metrology tools and the machine-learning predictor component calculates a critical dimension inference from measured spectra. Theoretical spectra are then generated by the predictor component based upon a modification of the critical dimension inference. The measured spectra are compared to the theoretical spectra and the fit of the measured spectra to the theoretical spectra is evaluated for acceptance. The results of the comparison and analysis is output in human readable form.Type: ApplicationFiled: January 4, 2023Publication date: June 13, 2024Inventors: Yun-Chung Teng, Jan-Hau Chang, Hsien-Hung Chang, Ming-Hsiung Fu
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Publication number: 20240190050Abstract: A bicycle component includes a composite laminate. The composite laminate includes a hollow container made of a first polymer-based material, a layer of a second polymer-based material disposed on the hollow container, and a layer of a composite material disposed on the layer of the second polymer-based material. The bicycle component also includes a water soluble core material disposed within hollow container.Type: ApplicationFiled: December 8, 2023Publication date: June 13, 2024Applicant: SRAM, LLCInventors: CHIA CHANG CHANG, CHEN HSIUNG CHEN, HUAN CHING HSU, CHING HAN LIU, CHU CHEN WANG
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Patent number: 12005711Abstract: The method of the present disclosure includes steps of: (S1) providing a silicon substrate; (S2) arranging and disposing an active component layer by utilizing a first type photomask on at least two high-precision regions of each of a plurality of inkjet print head chip regions on the silicon substrate; (S3) arranging and disposing a passive component layer by utilizing a second type photomask on the active component layer; and (S4) cutting the silicon substrate according to the inkjet print head chip regions so as to form the plurality of narrow type inkjet print head chips.Type: GrantFiled: March 18, 2021Date of Patent: June 11, 2024Assignee: MICROJET TECHNOLOGY CO., LTD.Inventors: Hao-Jan Mou, Rong-Ho Yu, Cheng-Ming Chang, Hsien-Chung Tai, Wen-Hsiung Liao, Chi-Feng Huang, Yung-Lung Han
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Patent number: 12009216Abstract: A semiconductor structure includes a semiconductor fin extending from a substrate, a source/drain (S/D) feature disposed over the semiconductor fin, a silicide layer disposed over the S/D feature, where the silicide layer extends along a sidewall of the S/D feature, and an etch-stop layer (ESL) disposed along a sidewall of the silicide layer.Type: GrantFiled: July 25, 2023Date of Patent: June 11, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Chun-Hsiung Lin, Shih-Cheng Chen, Chih-Hao Wang, Jung-Hung Chang, Jui-Chien Huang
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Patent number: 12009215Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a substrate having a base portion and a fin portion over the base portion. The semiconductor device structure includes an epitaxial structure over the fin portion. The semiconductor device structure includes a dielectric fin over the base portion. The semiconductor device structure includes a silicide layer between the dielectric fin and the epitaxial structure. A void is between the silicide layer and the dielectric fin.Type: GrantFiled: April 21, 2023Date of Patent: June 11, 2024Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chun-Hsiung Lin, Jung-Hung Chang, Shih-Cheng Chen, Kuo-Cheng Chiang, Chih-Hao Wang
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Patent number: 12001571Abstract: A method of operating a user device includes: receiving a command from a user to power on the user device, wherein the user device includes information on a restricted zone associated with the user device; detecting, by a monitoring entity of the user device without involvement of any device external to the user device, whether the user device is located within the restricted zone in response to the user device being powered on and before an operating system of the user device is executed; and granting access of the user to the user device by the monitoring entity in response to detecting the user device as being within the restricted zone.Type: GrantFiled: November 3, 2022Date of Patent: June 4, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.Inventors: Wen-Chang Kuo, Chiang Kao, Kuo Hsiung Chen, Ho-Han Liu, Ti-Yen Yang, Jo-Chan Liu, Chi-Pin Wang, Yao-Hsiung Chang
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Publication number: 20240178076Abstract: A method includes providing a first substrate which has an active layer, a metal layer, a passivation layer disposed on the metal layer, a first patterned metal layer passing through the passivation layer to electrically connected to the active layer, an insulating layer disposed on the passivation layer, and a second patterned metal layer passing through the insulating layer to electrically connected to the first patterned metal layer. A part of the metal layer does not serve as a portion of a thin film transistor, but serves as a portion of a gate line. The method includes providing a second substrate supporting a plurality of elements, transferring at least one of the plurality of elements from the second substrate to the second patterned metal layer of the first substrate, and fixing the at least one of the plurality of elements to the first substrate.Type: ApplicationFiled: February 2, 2024Publication date: May 30, 2024Inventors: Chia-Hsiung CHANG, Ting-Kai HUNG, Hsiao-Lang LIN
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Publication number: 20240176901Abstract: The present disclosure discloses a simulating interface system, which is assembled with an electronic device and has an interface module and a simulating module. The interface module is connected with an external electronic device, and receives connection signals from the external electronic device; and the simulating module is connected with the interface module, and has a simulating unit and a management unit, wherein the simulating unit is used to simulate a use authority of the electronic device, and the management unit adjusts the use authority to provide to the external electronic device based on the connection signals. The simulating unit analogizes the use authority of the electronic device, and the management unit adjusts the use authority to provide to the external electronic device based on the connection signals from the external electronic device, so as to achieve effective protection.Type: ApplicationFiled: November 24, 2023Publication date: May 30, 2024Applicant: Lanto Electronic LimitedInventors: Chih-Hsiung CHANG, Chih-Wei SUN, Chia-Ching LIN
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Patent number: 11996483Abstract: The present disclosure provides a semiconductor device that includes a semiconductor fin disposed over a substrate, an isolation structure at least partially surrounding the fin, an epitaxial source/drain (S/D) feature disposed over the semiconductor fin, where an extended portion of the epitaxial S/D feature extends over the isolation structure, and a silicide layer disposed on the epitaxial S/D feature, where the silicide layer covers top, bottom, sidewall, front, and back surfaces of the extended portion of the S/D feature.Type: GrantFiled: December 14, 2022Date of Patent: May 28, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Pei-Hsun Wang, Chih-Chao Chou, Shih-Cheng Chen, Jung-Hung Chang, Jui-Chien Huang, Chun-Hsiung Lin, Chih-Hao Wang
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Publication number: 20240168084Abstract: A semiconductor structure is provided. The semiconductor structure includes at least one metal gate structure and a device to be tested. The metal gate structure is disposed on a substrate. The device to be tested is disposed on the metal gate structure and electrically separated from the metal gate structure. The device to be tested is heated by a heat generated when the metal gate structure is applied with a voltage.Type: ApplicationFiled: December 20, 2022Publication date: May 23, 2024Applicant: United Microelectronics Corp.Inventors: Jih-Shun Chiang, Wen-Chun Chang, Wen-Hsiung Ko, Sung-Nien Kuo, Kuan-Cheng Su
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Publication number: 20240170954Abstract: A motor control method for coupled an electronic vehicle is provided. The motor controller controls a motor and is powered by a battery. The motor control method includes: when a main relay of the motor controller suddenly breaks contact, in a first phase, feeding back a surge current into the battery to suppress the surge current by a diode and a first current limit resistor of a first protecting circuit of the motor controller; and, in a second phase, conducting a discharge switch of a second protecting circuit of the motor controller by a control unit of the motor controller, and releasing the surge current to a reference voltage range by the discharge switch and a second current limit resistor of the second protecting circuit.Type: ApplicationFiled: December 27, 2022Publication date: May 23, 2024Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTEInventors: Nan-Hsiung TSENG, Bing-Ren CHEN, Shin-Hung CHANG, Chin-Hone LIN
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Publication number: 20240171384Abstract: A device which can be implemented on a single packaged integrated circuit or a multichip module comprises a plurality of non-volatile memory cells, and logic to use a physical unclonable function to produce a key and to store the key in a set of non-volatile memory cells in the plurality of non-volatile memory cells. The physical unclonable function can use entropy derived from non-volatile memory cells in the plurality of non-volatile memory cells to produce a key. Logic is described to disable changes to data in the set of non-volatile memory cells, and thereby freeze the key after it is stored in the set.Type: ApplicationFiled: November 29, 2023Publication date: May 23, 2024Applicant: MACRONIX INTERNATIONAL CO., LTD.Inventors: Chun-Hsiung HUNG, Chin-Hung CHANG
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Patent number: 11990557Abstract: There is provided an optical sensor package including a substrate, a base layer, an optical detection region, a light source and a light blocking wall. The base layer is arranged on the substrate. The light detection region and the light source are arranged on the base layer. The light blocking wall is arranged on the base layer, and located between the light detection region and the light source to block light directly propagating from the light source to the light detection region.Type: GrantFiled: October 29, 2020Date of Patent: May 21, 2024Assignee: PIXART IMAGING INC.Inventors: Chi-Chih Shen, Kuo-Hsiung Li, Shang-Feng Hsieh, Jui-Cheng Chuang, Yi-Chang Chang
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Patent number: 11984385Abstract: The present disclosure is related to a lead frame structure. The lead frame structure includes a bottom board and a blocking wall. The bottom board has a first conductive portion and a second conductive portion. The first conductive portion separates from the second conductive portion. The first and second conductive portions are configured to electrically connect to a light source. The blocking wall is located on the bottom board, and the blocking wall surrounds an opening. The first and the second conductive portions are exposed from the opening. The first and the second conductive portions each have an extending portion. The extending portion extends beyond an external surface of the blocking wall in a horizontal direction.Type: GrantFiled: April 14, 2021Date of Patent: May 14, 2024Assignee: Jentech Precision Industrial Co., LTD.Inventors: Jian-Tsai Chang, Chin-Jui Yu, Chun-Hsiung Wang, Wei-Chi Lin
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Patent number: 11983475Abstract: A semiconductor device includes: M*1st conductors in a first layer of metallization (M*1st layer) and being aligned correspondingly along different corresponding ones of alpha tracks and representing corresponding inputs of a cell region in the semiconductor device; and M*2nd conductors in a second layer of metallization (M*2nd layer) aligned correspondingly along beta tracks, and the M*2nd conductors including at least one power grid (PG) segment and one or more of an output pin or a routing segment; and each of first and second ones of the input pins having a length sufficient to accommodate at most two access points; each of the access points of the first and second input pins being aligned to a corresponding different one of first to fourth beta tracks; and the PG segment being aligned with one of the first to fourth beta tracks.Type: GrantFiled: February 7, 2023Date of Patent: May 14, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Pin-Dai Sue, Po-Hsiang Huang, Fong-Yuan Chang, Chi-Yu Lu, Sheng-Hsiung Chen, Chin-Chou Liu, Lee-Chung Lu, Yen-Hung Lin, Li-Chun Tien, Yi-Kan Cheng
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Publication number: 20240143264Abstract: Disclosed is a wireless transmission system, including a mobile electronic device with first screen information, a computer with second screen information, and a docking station coupled to the computer. When accommodating the mobile electronic device, the docking station transmits an electrical signal to the mobile electronic device, wherein the computer confirms that the mobile electronic device is located on the docking station according to a Bluetooth Low Energy signal sent by the mobile electronic device, the computer transmits Wi-Fi service set identification information to the mobile electronic device through a Bluetooth Low Energy protocol, the computer and the mobile electronic device are connected to the same Wi-Fi access point, and the mobile electronic device sends the first screen information back to the computer. Accordingly, the problem that the computer and the mobile electronic device cannot transmit data or screen information to each other through a transmission line is solved.Type: ApplicationFiled: July 21, 2023Publication date: May 2, 2024Applicant: Lanto Electronic LimitedInventors: Chih-Hsiung CHANG, Chia-Ching LIN
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Publication number: 20240145389Abstract: A semiconductor chip includes a first intellectual property block. There are a second intellectual property block and a third intellectual property block around the first intellectual property block. There is a multiple metal layer stack over the first intellectual property block, the second intellectual property block, and the third intellectual property block. An interconnect structure is situated in the upper portion of the multiple metal layer stack. The interconnect structure is configured for connecting the first intellectual property block and the second intellectual property block. In addition, at least a part of the interconnect structure extends across and over the third intellectual property block.Type: ApplicationFiled: July 28, 2023Publication date: May 2, 2024Inventors: Li-Chiu WENG, Yew Teck TIEO, Ming-Hsuan WANG, Chia-Cheng CHEN, Wei-Yi CHANG, Jen-Hang YANG, Chien-Hsiung HSU
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Patent number: 11961762Abstract: A method includes forming a first conductive feature, depositing a passivation layer on a sidewall and a top surface of the first conductive feature, etching the passivation layer to reveal the first conductive feature, and recessing a first top surface of the passivation layer to form a step. The step comprises a second top surface of the passivation layer. The method further includes forming a planarization layer on the passivation layer, and forming a second conductive feature extending into the passivation layer to contact the first conductive feature.Type: GrantFiled: June 30, 2022Date of Patent: April 16, 2024Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Ming-Da Cheng, Tzy-Kuang Lee, Song-Bor Lee, Wen-Hsiung Lu, Po-Hao Tsai, Wen-Che Chang
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Patent number: 11961892Abstract: A semiconductor device and methods of forming the same are disclosed. The semiconductor device includes a substrate, first and second source/drain (S/D) regions, a channel between the first and second S/D regions, a gate engaging the channel, and a contact feature connecting to the first S/D region. The contact feature includes first and second contact layers. The first contact layer has a conformal cross-sectional profile and is in contact with the first S/D region on at least two sides thereof. In embodiments, the first contact layer is in direct contact with three or four sides of the first S/D region so as to increase the contact area. The first contact layer includes one of a semiconductor-metal alloy, an III-V semiconductor, and germanium.Type: GrantFiled: June 10, 2022Date of Patent: April 16, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Carlos H. Diaz, Chung-Cheng Wu, Chia-Hao Chang, Chih-Hao Wang, Jean-Pierre Colinge, Chun-Hsiung Lin, Wai-Yi Lien, Ying-Keung Leung