Abstract: A method for semiconductor self-aligned patterning includes steps of providing a substrate comprising a first layer and a second layer, wherein the first layer is on top of the second layer; removing a portion of the first layer to form a first pattern; depositing a first conformal layer on the first pattern; depositing a second conformal layer on the first conformal layer; removing a portion of the second conformal layer to expose a portion of the first conformal layer; and thinning the first conformal layer and the second conformal layer alternatively to form a second pattern. A semiconductor self-aligned structure is also provided.

Abstract: A method for semiconductor self-aligned patterning includes steps of providing a substrate comprising a first layer and a second layer, wherein the first layer is on top of the second layer; removing a portion of the first layer to form a first pattern; depositing a first conformal layer on the first pattern; depositing a second conformal layer on the first conformal layer; removing a portion of the second conformal layer to expose a portion of the first conformal layer; and thinning the first conformal layer and the second conformal layer alternatively to form a second pattern. A semiconductor self-aligned structure is also provided.

Abstract: A method for wafer alignment includes the following steps. First, a wafer including a first material layer and a second material layer on the top of the first material layer is provided, wherein the first material layer includes a first alignment mark. Then, the wafer is aligned in an exposure tool. After that, the second material layer is patterned to form a second alignment mark. Finally, an offset distance between the first alignment mark and the second alignment mark is measured in the exposure tool.

Abstract: An alignment mark arrangement includes: a first alignment pattern comprising a plurality of parallel first stripes on a substrate, wherein each of the first stripes includes a first dimension; and a second alignment pattern positioned directly above and overlapping with the first alignment pattern, the second alignment pattern including a plurality of parallel second stripes, wherein each of the second stripes of the second alignment pattern has a second dimension that is larger than the first dimension of each of the first stripes of the first alignment pattern.

Abstract: A method for forming a semiconductor device is disclosed. A substrate comprising a structural layer thereon is provided. A hard mask layer is formed on the structural layer. A photoresist layer is formed on the hard mask layer. The photoresist layer is patterned to from a plurality of main photoresist patterns and at least one dummy photoresist pattern between the main photoresist patterns or adjacent to one of the main photoresist patterns, wherein width of the dummy photoresist pattern is less than that of the main photoresist patterns. Two main photoresist patterns are separated with each other by a first opening, and two dummy photoresist patterns are separated with each other by a second opening. Width of the second opening is less than that of the first opening. The hard mask layer is patterned using the patterned photoresist layer as a mask. The structural layer is patterned using the patterned hard mask layer as a mask.

Abstract: An alignment mark arrangement includes: a first alignment pattern comprising a plurality of parallel first stripes on a substrate, wherein each of the first stripes includes a first dimension; and a second alignment pattern positioned directly above and overlapping with the first alignment pattern, the second alignment pattern including a plurality of parallel second stripes, wherein each of the second stripes of the second alignment pattern has a second dimension that is larger than the first dimension of each of the first stripes of the first alignment pattern.

Abstract: A method for fabricating the semiconductor device comprises providing a semiconductor substrate having a device region and a testkey region. A first trench is formed in the device region and a second trench is formed in the testkey region. A conductive layer with a first etching selectivity is formed in the first and second trenches. A first implantation process is performed in a first direction to form a first doped region with a first impurity and an undoped region in the conductive layer simultaneously and respectively in the device region and in the testkey region. A second implantation process is performed in the second trench to form a second doped region with a second impurity in the conductive layer, wherein the conductive layer in the second trench has a second etching selectivity higher than the first etching selectivity.

Abstract: A method for wafer alignment includes the following steps. First, a wafer including a first material layer and a second material layer on the top of the first material layer is provided, wherein the first material layer includes a first alignment mark. Then, the wafer is aligned in an exposure tool. After that, the second material layer is patterned to form a second alignment mark. Finally, an offset distance between the first alignment mark and the second alignment mark is measured in the exposure tool.

Abstract: A small-size (w<0.5 micrometers) alignment mark in combination with a “k1 process” is proposed, which is particularly suited for the fabrication of trench-capacitor DRAM devices which requires highly accurate AA-DT and GC-DT overlay alignment. The “k1 process” is utilized to etch away polysilicon studded in the alignment mark trenches and to refresh the trench profile, thereby improving overlay alignment accuracy and precision.

Abstract: A method for fabricating the semiconductor device comprises providing a semiconductor substrate having a device region and a testkey region. A first trench is formed in the device region and a second trench is formed in the testkey region. A conductive layer with a first etching selectivity is formed in the first and second trenches. A first implantation process is performed in a first direction to form a first doped region with a first impurity and an undoped region in the conductive layer simultaneously and respectively in the device region and in the testkey region. A second implantation process is performed in the second trench to form a second doped region with a second impurity in the conductive layer, wherein the conductive layer in the second trench has a second etching selectivity higher than the first etching selectivity.

Abstract: A method for forming a semiconductor device is disclosed. A substrate comprising a structural layer thereon is provided. A hard mask layer is formed on the structural layer. A photoresist layer is formed on the hard mask layer. The photoresist layer is patterned to from a plurality of main photoresist patterns and at least one dummy photoresist pattern between the main photoresist patterns or adjacent to one of the main photoresist patterns, wherein width of the dummy photoresist pattern is less than that of the main photoresist patterns. Two main photoresist patterns are separated with each other by a first opening, and two dummy photoresist patterns are separated with each other by a second opening. Width of the second opening is less than that of the first opening. The hard mask layer is patterned using the patterned photoresist layer as a mask. The structural layer is patterned using the patterned hard mask layer as a mask.

Abstract: A small-size (w<0.5 micrometers) alignment mark in combination with a “k1 process” is proposed, which is particularly suited for the fabrication of trench-capacitor DRAM devices which requires highly accurate AA-DT alignment. The “k1 process” is utilized to etch away polysilicon studded in the alignment mark trenches and refresh the trench profile prior to AA pattern transferring, thereby improving wafer alignment accuracy and precision.

Abstract: A small-size (w<0.5 micrometers) alignment mark in combination with a “k1 process” is proposed, which is particularly suited for the fabrication of trench-capacitor DRAM devices which requires highly accurate AA-DT and GC-DT overlay alignment. The “k1 process” is utilized to etch away polysilicon studded in the alignment mark trenches and to refresh the trench profile, thereby improving overlay alignment accuracy and precision.

Abstract: A small-size (w<0.5 micrometers) alignment mark in combination with a “k1 process” is proposed, which is particularly suited for the fabrication of trench-capacitor DRAM devices which requires highly accurate AA-DT alignment. The “k1 process” is utilized to etch away polysilicon studded in the alignment mark trenches and refresh the trench profile prior to AA pattern transferring, thereby improving wafer alignment accuracy and precision.