Patents by Inventor An-Hsuan HSU

An-Hsuan HSU has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250038078
    Abstract: A bonding structure and a package structure are provided. The bonding structure includes a first pad and a plurality of first wires. The first pad has a top surface including a first region and a second region, wherein the second region is closer to an edge of the top surface of the first pad than the first region is. The first wires are on the top surface of the first pad, wherein a number of the first wires on the first region is greater than a number of the first wires on the second region.
    Type: Application
    Filed: July 28, 2023
    Publication date: January 30, 2025
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: An-Hsuan HSU, Chin-Li KAO
  • Publication number: 20240413061
    Abstract: A package structure is provided. The package structure includes a substrate, a wiring structure, and a wire bundle structure. The wiring structure is over the substrate. The wire bundle structure is between the wiring structure and the substrate. The wire bundle structure includes a first wire bundle extending from the substrate and a second wire bundle extending from the wiring structure and contacting the first nanowire bundle. The wire bundle structure is configured to reduce a variation in a distance of a gap between the substrate and the wiring structure.
    Type: Application
    Filed: June 7, 2023
    Publication date: December 12, 2024
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: An-Hsuan HSU, Cheng-Yuan KUNG, Yaohsin CHOU
  • Patent number: 12113044
    Abstract: A semiconductor device package and a fabrication method thereof are disclosed. The semiconductor package comprises: a package component having a first mounting surface and a second mounting surface; and a first electronic component having a first conductive pad signal communicatively mounted on the first mounting surface through a first type connector; wherein the first type connector comprises a first solder composition having a lower melting point layer sandwiched between a pair of higher melting point layers, wherein the lower melting point layer is composed of alloys capable of forming a room temperature eutectic.
    Type: Grant
    Filed: February 18, 2022
    Date of Patent: October 8, 2024
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Shan-Bo Wang, Chin-Li Kao, An-Hsuan Hsu
  • Publication number: 20240334586
    Abstract: A package structure is provided. The package structure includes an electronic component, a heat dissipating element, a thermal interfacing unit, and a confining structure. The electronic component has an upper surface. The heat dissipating element is over the upper surface of the electronic component. The thermal interfacing unit is between the upper surface of the electronic component and the heat dissipating element. The thermal interfacing unit includes a thermal interfacing material (TIM). The TIM is attached to the confining structure by capillary force.
    Type: Application
    Filed: March 31, 2023
    Publication date: October 3, 2024
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: An-Hsuan HSU, Hung-Hsien HUANG, Chin-Li KAO
  • Publication number: 20240304450
    Abstract: An electronic package structure includes a first electronic component, a first thermal conductive structure and a second thermal conductive structure. The first thermal conductive structure is disposed over the first electronic component. The second thermal conductive structure is disposed between the first electronic component and the first thermal conductive structure. A first heat transfer rate of the second thermal conductive structure along a first direction from the first electronic component to the first thermal conductive structure is greater than a second heat transfer rate of the second thermal conductive structure along a second direction nonparallel with the first direction from the first electronic component to an element other than the first thermal conductive structure.
    Type: Application
    Filed: March 7, 2023
    Publication date: September 12, 2024
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: An-Hsuan HSU, Chin-Li KAO
  • Patent number: 12057670
    Abstract: A semiconductor package structure and a method for manufacturing a semiconductor package structure are provided. The semiconductor package structure includes a first substrate, a second substrate, and a solid solution layer. The first substrate includes a first metal layer, and the first metal layer includes a first metal. The second substrate includes a second metal layer. The solid solution layer electrically connects the first metal layer to the second metal layer. The solid solution layer includes a first metal-rich layer.
    Type: Grant
    Filed: March 31, 2021
    Date of Patent: August 6, 2024
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: An-Hsuan Hsu, Yung-Sheng Lin
  • Publication number: 20240063159
    Abstract: A package structure is disclosed. The package structure includes a substrate including a conductive element and a plurality of wires having a surface area through which heat of the conductive element can be dissipated, lowering a bonding temperature of the conductive element. The package structure also includes a conductive layer disposed between the conductive element of the substrate and the plurality of wires. The conductive contact layer attaches the plurality of wires over the conductive element.
    Type: Application
    Filed: August 19, 2022
    Publication date: February 22, 2024
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: An-Hsuan HSU, Chin-Li KAO
  • Patent number: 11798907
    Abstract: A semiconductor package includes a first substrate, a first flow channel and a second flow channel. The first flow channel is on the first substrate. The second flow channel is on the first substrate and in fluid communication with the first flow channel. The second flow channel is spaced from an inlet and an outlet of the first flow channel. The first flow channel and the second flow channel constitute a bonding region of the first substrate.
    Type: Grant
    Filed: November 6, 2020
    Date of Patent: October 24, 2023
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Yung-Sheng Lin, Yun-Ching Hung, An-Hsuan Hsu, Chung-Hung Lai
  • Publication number: 20230268314
    Abstract: A semiconductor device package and a fabrication method thereof are disclosed. The semiconductor package comprises: a package component having a first mounting surface and a second mounting surface; and a first electronic component having a first conductive pad signal communicatively mounted on the first mounting surface through a first type connector; wherein the first type connector comprises a first solder composition having a lower melting point layer sandwiched between a pair of higher melting point layers, wherein the lower melting point layer is composed of alloys capable of forming a room temperature eutectic.
    Type: Application
    Filed: February 18, 2022
    Publication date: August 24, 2023
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Shan-Bo WANG, Chin-Li KAO, An-Hsuan HSU
  • Publication number: 20220320760
    Abstract: A semiconductor package structure and a method for manufacturing a semiconductor package structure are provided. The semiconductor package structure includes a first substrate, a second substrate, and a solid solution layer. The first substrate includes a first metal layer, and the first metal layer includes a first metal. The second substrate includes a second metal layer. The solid solution layer electrically connects the first metal layer to the second metal layer. The solid solution layer includes a first metal-rich layer.
    Type: Application
    Filed: March 31, 2021
    Publication date: October 6, 2022
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: An-Hsuan HSU, Yung-Sheng LIN
  • Publication number: 20220148989
    Abstract: A semiconductor package includes a first substrate, a first flow channel and a second flow channel. The first flow channel is on the first substrate. The second flow channel is on the first substrate and in fluid communication with the first flow channel. The second flow channel is spaced from an inlet and an outlet of the first flow channel. The first flow channel and the second flow channel constitute a bonding region of the first substrate.
    Type: Application
    Filed: November 6, 2020
    Publication date: May 12, 2022
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Yung-Sheng LIN, Yun-Ching HUNG, An-Hsuan HSU, Chung-Hung LAI