Abstract: An example compute cabinet assembly includes an equipment room configured to implement electrical components therein, an air inlet channel coupled to a first side of the equipment room, and a cabinet fan module coupled to a second side of the equipment room opposite the first side. A first air outlet channel is coupled to the cabinet fan module and extends along a third side of the equipment room towards a first outlet of the first air outlet channel. Moreover, electric fans are positioned in the cabinet fan module, the electric fans being configured to create an airflow path originating at an inlet of the air inlet channel. The airflow path further extends through the equipment room and cabinet fan module. A guide plate is also positioned adjacent to an inlet of the equipment room, the guide plate being configured to uniformly distribute the airflow path through the equipment room.

Abstract: A memory circuit includes a substrate with a front side and a back side opposite the front side. An interconnect structure is situated on or over the substrate and has first and second metal layers and a via electrically connecting the first and second metal layers. A word line driver circuit is configured to output a word line enable signal to a word line of a memory array. The word line driver circuit has an inverter circuit configured to receive a word line signal, and an enable transistor electrically connected to an output of the inverter circuit by a metal line that includes the first metal layer, the second metal layer, and the via.

Abstract: A memory device for CIM, applicable to a 3D AND-type flash memory, includes a memory array, input word line pairs, and a signal processing circuit. The memory array includes first and second pairs of memory cells. Each first pair of memory cells includes a first memory cell set coupled to a first GBL and a second memory cell set coupled to a second GBL. Each second pair of memory cells includes a third memory cell set coupled to the first GBL and a fourth memory cell set coupled to the second GBL. Each input word line pair includes a first input word line coupled to the first and the second memory cell sets, and a second input word line coupled to the third and the fourth memory cell sets s. The signal processing circuit is coupled to the first and second global bit lines.

Abstract: A polygonal three-dimensional building blocks comprises: a main body having a central area and at least three abutment side walls, the central area located among the abutment side walls; the abutment side walls connected to each other in a ring shape and having a slanted surface respectively, each one of the abutment side walls having a first side edge and a second side edge respectively, the first side edge and the second side edge arranged at two opposite sides of each one of the abutment side wall, the central area located between the first side edges of the abutment side walls, the abutment side walls having an inner surface and an outer abutment surface opposite from each other; the main body having a plurality of magnetic attachment areas; a plurality of magnetic members installed at the magnetic attachment areas.

Abstract: A magnetic memory including a substrate, a spin-orbit torque (SOT) layer, a magnetic tunnel junction (MTJ) stack, a first protection layer, and a second protection layer is provided. The SOT layer is located over the substrate. The MTJ stack is located on the SOT layer. The first protection layer and the second protection layer are located on the sidewall of the MTJ stack. The first protection layer is located between the second protection layer and the MTJ stack. There is a notch between the second protection layer and the SOT layer.

Abstract: Color filter array patterns are provided for enhancing an image sensor's light sensitivity while preserving a color accuracy for image signal processing applications. In one example, an image sensor can include a substrate layer containing a first set of photodiodes and a second set of photodiodes, wherein each of the first set of photodiodes is larger than each of the second set of photodiodes; a first color filter array (CFA) covering the first set of photodiodes, wherein the first CFA includes a first set of color filters and a portion of the first set of color filters includes one or more clear filters; a second CFA covering the second set of photodiodes, wherein the second CFA includes a second set of color filters that is different than the first set of color filters; and one or more lenses covering the first CFA and the second CFA.

Abstract: A bonding structure and a package structure are provided. The bonding structure includes a first pad and a plurality of first wires. The first pad has a top surface including a first region and a second region, wherein the second region is closer to an edge of the top surface of the first pad than the first region is. The first wires are on the top surface of the first pad, wherein a number of the first wires on the first region is greater than a number of the first wires on the second region.

Abstract: Provided herein are antibodies or antigen binding fragments thereof having a binding specificity for p95HER2 or for CD73, bispecific antibodies comprising a first antigen binding region that binds to p95HER2 or CD73 and a second antigen binding region that binds to an immune checkpoint molecule or an immune stimulatory molecule, and antibody-drug conjugates thereof. Also provided herein are pharmaceutical compositions comprising the antibodies, antigen binding fragments thereof, bispecific antibodies or antibody drug conjugates thereof, and methods of use thereof. The methods of use include method of treating cancer.

Abstract: A memory device, such as a 3D AND flash memory, includes a memory cell block, a word line driver, and a plurality of bit line switches. The word line driver has a plurality of complementary transistor pairs for respectively generating a plurality of word line signals for a plurality of word lines. Substrates of a first transistor and a second transistor of each of the complementary transistor pairs respectively receive a first voltage and a second voltage. Each of the bit line switches includes a third transistor. A substrate of the third transistor receives a third voltage. The first voltage, the second voltage, and the third voltage are constant static voltages during a soft program operation and a soft program verify operation.

Abstract: A plasma enhanced chemical vapor deposition (PECVD) method includes loading a wafer having a magnetic layer thereon into a processing chamber equipped with a radio frequency (RF) system, introducing an aromatic hydrocarbon precursor into the processing chamber, and turning on an RF source of the RF system to decompose the aromatic hydrocarbon precursor into active radicals at a frequency greater than about 1000 Hz to form a graphene layer over the magnetic layer.

Abstract: A cooling tower with a hydroelectric power generation unit includes a tower body, a water spraying device, and a water guiding plate, in addition to the hydroelectric power generation unit. The tower body has a water collection tank divided into a water-collecting tank area and a power-generating tank area. The water sprayed out by the water spraying device is guided by the water guiding plate into the water-collecting tank area. When the water-collecting tank area is full, the water in the water-collecting tank area flows into the power-generating tank area through the partition portion, or more particularly through the hydroelectric power generation unit, such that the hydroelectric power generation unit generates electricity from a difference in water level. By directly converting the potential energy of cooled cooling water into electric energy that can be stored or used, the cooling tower saves energy and contributes to environmental protection.

Abstract: A package structure is provided. The package structure includes a substrate, a wiring structure, and a wire bundle structure. The wiring structure is over the substrate. The wire bundle structure is between the wiring structure and the substrate. The wire bundle structure includes a first wire bundle extending from the substrate and a second wire bundle extending from the wiring structure and contacting the first nanowire bundle. The wire bundle structure is configured to reduce a variation in a distance of a gap between the substrate and the wiring structure.

Abstract: Capture membranes for lanthanide metal ions can be made from fusion proteins having at least one lanthanide metal binding sequence (SEQ ID NO: 1-4) covalently bound to a silk-elastin-like polymer (SELP). Capture membranes can be made from silk nanofibrils that are surface-modified with a lanthanide metal binding molecule. The capture membranes can have a layered structure or can contained cross-linked peptides in a hydrogel.

Abstract: An apparatus, semiconductor device and method of manufacture are presented, wherein a hard mask layer and one or more etch stop layers are etched in an etching chamber. In an embodiment the semiconductor device is placed on a mounting platform at a first height and an etch process is performed, then the semiconductor device is moved to a second height within the chamber and a second etch process is performed, with the rotational speed of the semiconductor device reduced during movements in order to reduce the chance of cross contamination.

Abstract: A card connecting assembly mountable on a circuit board for insertion of an electronic card includes a card connector disposed on the circuit board, and an electronic card mounting structure having first and second guiderails for the electronic card to be slidably insertable thereinto, and a latch mechanism integrally formed and elastically connected with the first guiderail. The latch mechanism includes an operating portion and a latch portion. With the latch portion engaged in the notch when the electronic card is inserted into the card connector to prevent removal thereof. Through the operating portion operably and elastically displaced away from the first guiderail, the latch portion is disengageable from the notch, the electronic card is permitted to be removed from the card connector.

Abstract: The main objective of the present invention is to provide a lactic acid bacterial strain and a composition for improving gut microbiota composition. The composition comprises the lactic acid bacterial strain and/or extracellular vesicles secreted by the lactic acid bacterial strain. Another objective of the present invention is to provide a method for improving gut microbiota composition and products of the lactic acid bacterial strain. Additionally, the composition of the present invention has the capability to influence the growth of Firmicutes and Bacteroidetes, thereby leading to an improvement in gut microbiota composition.

Abstract: A locking mechanism for removably locking a first electrical component to a second electrical component includes a positioning post secured to the second electrical component, a frame for mounting the first electrical component, and a locking member movably connected with the frame. The positioning post has a head and a neck. The locking member has a snap fastening portion, a flexible portion and an unlocking operated portion. When the snap fastening portion contacts the head and is moved toward the neck, a lateral thrust force exerted by the head spreads the snap fastening portion and cause deformation of the flexible portion to store a biasing restoring force. When the snap fastening portion is aligned with the neck, the snap fastening portion is moved by the biasing restoring force to be snap fastened to the neck. The unlocking operated portion is operated to disengage the snap fastening portion from the neck.

Abstract: A semiconductor device package and a fabrication method thereof are disclosed. The semiconductor package comprises: a package component having a first mounting surface and a second mounting surface; and a first electronic component having a first conductive pad signal communicatively mounted on the first mounting surface through a first type connector; wherein the first type connector comprises a first solder composition having a lower melting point layer sandwiched between a pair of higher melting point layers, wherein the lower melting point layer is composed of alloys capable of forming a room temperature eutectic.

Abstract: An apparatus, semiconductor device and method of manufacture are presented, wherein a hard mask layer and one or more etch stop layers are etched in an etching chamber. In an embodiment the semiconductor device is placed on a mounting platform at a first height and an etch process is performed, then the semiconductor device is moved to a second height within the chamber and a second etch process is performed, with the rotational speed of the semiconductor device reduced during movements in order to reduce the chance of cross contamination.

Abstract: A package structure is provided. The package structure includes an electronic component, a heat dissipating element, a thermal interfacing unit, and a confining structure. The electronic component has an upper surface. The heat dissipating element is over the upper surface of the electronic component. The thermal interfacing unit is between the upper surface of the electronic component and the heat dissipating element. The thermal interfacing unit includes a thermal interfacing material (TIM). The TIM is attached to the confining structure by capillary force.