Abstract: The present invention relates to a method for measuring muscle mass, including: a first selection step, wherein a frame selection information is obtained by using a frame to select a fascia region from a provided computed tomography image under the condition that the window width ranges from 300 HU to 500 HU and the window level ranges from 40 HU to 50 HU, wherein the selected range of the fascia region includes a muscle; and a second selection step, wherein a muscle information of the muscle is obtained by calculating a pixel value in the frame-selected fascia region under the condition that the HU value of the CT image ranges from ?29 HU to 150 HU.

Abstract: A method for detecting defects in a semiconductor structure is provided. The method includes the following operations. A semiconductor structure having a plurality of conductive structures is received. An electron beam inspection operation is performed on the plurality of conductive structures of the semiconductor structure to obtain an inspection data, wherein a pulsed electron beam utilized in the electron beam inspection operation is selected from the group consisting of a nanosecond pulsed beam, a picosecond pulsed beam, and a femtosecond pulsed beam. A first conductive structure having a non-open defect is identified from the inspection data. A method for classifying semiconductor structure is also provided.

Abstract: One aspect of the present disclosure pertains to a method of forming a semiconductor structure. The method includes forming an active region over a substrate, forming a dummy gate layer over the active region, forming a hard mask layer over the dummy gate layer, forming a patterned photoresist over the hard mask layer, and performing an etching process to the hard mask layer and the dummy gate layer using the patterned photoresist, thereby forming patterned hard mask structures and patterned dummy gate structures. The patterned hard mask structures are formed with an uneven profile having a protruding portion. The protruding portion of each of the patterned hard mask structures has a first width, wherein each of the patterned dummy gate structures has a second width, and the first width is greater than the second width.

Abstract: Persistent storage contains a parent table and one or more child tables, the parent table containing: a class field specifying types, and one or more filter fields. One or more processors may: receive a first request to read first information of a first type for a first entity; determine that, in a first entry of the parent table for the first entity, the first type is specified in the class field; obtain the first information from a child table associated with the first type; receive a second request to read second information of a second type for a second entity; determine that, in a second entry of the parent table for the second entity, the second type is indicated as present by a filter field that is associated with the second type; and obtain the second information from a set of additional fields in the second entry.

Abstract: An apparatus, system and method for storing die carriers and transferring a semiconductor die between the die carriers. A die stocker includes a rack enclosure with an integrated sorting system. The rack enclosure includes storage cells configured to receive and store die carriers having different physical configurations. A transport system transports first and second die carriers between a first plurality of storage cells and a first sorter load port, where the transport system introduces the first and second die carriers to a first sorter. The transport system transports third and fourth die carriers between a second plurality of storage cells and a second sorter load port, where the transport system introduces the third and fourth die carriers to a second sorter. The first and second die carriers have a first physical configuration, and the third and fourth die carriers have a second physical configuration, different than the first physical configuration.

Abstract: An integrated circuit (IC) chip with polish stop layers and a method of fabricating the IC chip are disclosed. The method includes forming a first IC chip having a device region and a peripheral region. Forming the first IC chip includes forming a device layer on a substrate, forming an interconnect structure on the device layer, depositing a first dielectric layer on a first portion of the interconnect structure in the peripheral region, depositing a second dielectric layer on the first dielectric layer and on a second portion of the interconnect structure in the device region, and performing a polishing process on the second dielectric layer to substantially coplanarize a top surface of the second dielectric layer with a top surface of the first dielectric layer. The method further includes performing a bonding process on the second dielectric layer to bond a second IC chip to the first IC chip.

Abstract: A method and a device for scheduling charging. The method includes the following steps: multiple charging records are collected; multiple charging time data of the charging records of which charging duration is within a predetermined time range is extracted from the collected charging records; and the charging time data is analyzed by using a way of weight point to obtain a suggestion charging period.

Abstract: A display device including a display module and a backlight module is provided. The display module has a display region. The backlight module is overlapped with the display module and includes a plurality of light emitting diodes. The plurality of light emitting diodes form a light emitting region. The light emitting region is overlapped with the display region, and an area of the light emitting region is larger than an area of the display region.

Abstract: The disclosure relates to methods, apparatuses, and systems of providing livestream services involving multiple camera angles. A video streaming system may provide a client with a data stream that allows for viewing the video streaming from any of the multiple cameras at the client's choosing. The video streaming system may first access image data from the multiple cameras. Image data from the multiple cameras taken at a single instance in time may be “stitched” together into a single array of image data to form an “image wall.” The image wall may be compressed to be substantially smaller than the sum of their individual compressed images. A stream of image walls may be generated and transmitted to a client device. Metadata including mapping information enables the client to locate a chosen camera angle to view and switch to any camera angle viewing of the same video stream at the client's choosing.

Abstract: The present disclosure provides a method for manufacturing a semiconductor. The method includes: forming a metal oxide layer over a gate structure over a substrate; forming a dielectric layer over the metal oxide layer; forming a metal layer over the metal oxide layer; and performing a chemical mechanical polish (CMP) operation to remove a portion of the dielectric layer and a portion of the metal layer, the CMP operation stopping at the metal oxide layer, wherein a slurry used in the CMP operation includes a ceria compound. The present disclosure also provides a method for planarizing a metal-dielectric surface.

Abstract: A package structure includes a carrier substrate, a die, and an encapsulant. The carrier substrate includes through carrier vias (TCV). The die is disposed over the carrier substrate. The die includes a semiconductor substrate and conductive posts disposed over the semiconductor substrate. The conductive posts face away from the carrier substrate. The encapsulant laterally encapsulates the die.

Abstract: An electronic device is provided. The electronic device includes an electronic unit, a vehicle control unit and a sensing unit. The electronic unit includes a light-emitting unit that provides a first emitted light and a first light-filtering unit disposed on the light-emitting unit. The first light-filtering unit includes a substrate and a first light-conversion layer disposed on the substrate. The vehicle control unit is electrically connected to the light-emitting unit. The sensing unit is electrically connected to the vehicle control unit. The vehicle control unit modulates the intensity of the first emitted light based on the sensing signal from the sensing unit. The modulated first emitted light passes through the first light-filtering unit to form a second emitted light.

Abstract: An audio signal enhancement system is disclosed. The audio signal enhancement system includes a neural network-like human voice detection module and a frequency shifting module. The neural network-like human voice detection module is used to detect a human voice of an input signal it receives. The frequency shifting module is coupled to the neural network-like human voice detection module and used to perform a frequency shifting process on the human voice to generate an enhanced human voice.

Abstract: A method of manufacturing an interconnect structure includes forming an opening through a dielectric layer. The opening exposes a top surface of a first conductive feature. The method further includes forming a barrier layer on sidewalls of the opening, passivating the exposed top surface of the first conductive feature with a treatment process, forming a liner layer over the barrier layer, and filling the opening with a conductive material. The liner layer may include ruthenium.

Abstract: A method of manufacturing a FinFET includes at last the following steps. A semiconductor substrate is patterned to form trenches in the semiconductor substrate and semiconductor fins located between two adjacent trenches of the trenches. Gate stacks is formed over portions of the semiconductor fins. Strained material portions are formed over the semiconductor fins revealed by the gate stacks. First metal contacts are formed over the gate stacks, the first metal contacts electrically connecting the strained material portions. Air gaps are formed in the FinFET at positions between two adjacent gate stacks and between two adjacent strained materials.

Abstract: A method of manufacturing an interconnect structure includes forming an opening through a dielectric layer. The opening exposes a top surface of a first conductive feature. The method further includes forming a barrier layer on sidewalls of the opening, passivating the exposed top surface of the first conductive feature with a treatment process, forming a liner layer over the barrier layer, and filling the opening with a conductive material. The liner layer may include ruthenium.

Abstract: A system and method for cleaning ring frames is disclosed. In one embodiment, a ring frame processing system includes: a plurality of blades for mechanically removing tapes and tape residues from surfaces of a ring frame; a plurality of wheel brushes for conditioning the surfaces of the ring frame; and a transport mechanism for transporting the ring frame.

Abstract: A system booting method for a computer system having a plurality of central processing units and a booting unit is disclosed. The system booting method includes determining, by the booting unit, a booting mode of the computer system; transmitting a booting signal, which is related to the booting mode, to the plurality of CPUs of the computer system; and entering a multi-CPU booting mode or entering an independent booting mode of the plurality CPUs according to the booting signal.

Abstract: A memory device includes first transistor over a semiconductor substrate, wherein the first transistor includes a first word line extending over the semiconductor substrate; a second transistor over the semiconductor substrate, wherein the second transistor includes a second word line extending over the first word line; a first air gap extending between the first word line and the second word line; a memory film extending along and contacting the first word line and the second word line; a channel layer extending along the memory film; a source line extending along the channel layer, wherein the memory film is between the source line and the word line; a bit line extending along the channel layer, wherein the memory film is between the bit line and the word line; and an isolation region between the source line and the bit line.

Abstract: Interconnect structures exhibiting reduced accumulation of copper vacancies along interfaces between contact etch stop layers (CESLs) and interconnects, along with methods for fabrication, are disclosed herein. A method includes forming a copper interconnect in a dielectric layer and depositing a metal nitride CESL over the copper interconnect and the dielectric layer. An interface between the metal nitride CESL and the copper interconnect has a first surface nitrogen concentration, a first nitrogen concentration and/or a first number of nitrogen-nitrogen bonds. A nitrogen plasma treatment is performed to modify the interface between the metal nitride CESL and the copper interconnect.