Patents by Inventor An-Hsun Lo
An-Hsun Lo has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20250020570Abstract: A method for inspecting particles is suitable for inspecting particles on a substrate. The method for inspecting the particles includes the following. The substrate is disposed on a stage. An inspection radiation is provided to irradiate on the substrate, in which the inspection radiation is suitable for exciting the particles on the substrate to emit a secondary radiation. Also, the secondary radiation is detected to confirm whether the particles exist on the substrate and positions of the particles are detected.Type: ApplicationFiled: April 9, 2024Publication date: January 16, 2025Applicant: National Tsing Hua UniversityInventors: Tsai-Sheng Gau, Burn Jeng Lin, Po-Hsiung Chen, Po-Hsun Lu, Meng-Chen Lo
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Publication number: 20250023383Abstract: A control method applied to a power supply system. The power supply system comprises at least one first power unit and a second power unit, and the at least one first power unit is configured to provide power to an electrical load according to a power provided by a power source. The control method comprises: detecting a load status of the power supply system; when the load status is determined to be a peak load, generating a trigger signal; and in response to the trigger signal, disabling a first-stage converter in the second power unit, and controlling an energy storage capacitor in the second power unit to provide power to the electrical load, wherein the energy storage capacitor is coupled between the first-stage converter and a second-stage converter in the second power unit.Type: ApplicationFiled: July 12, 2024Publication date: January 16, 2025Inventors: Hsieh-Hsiung CHENG, Te-Chih PENG, Ming-Hsiang LO, Kuo-Hsun CHIEN
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Patent number: 12187806Abstract: The present invention relates to a novel antibody, an antigen-binding fragment thereof and the uses of the antibody and fragment, wherein the antibody and the fragment comprise specific complementarity-determining regions (CDRs) and/or specifically bind to human CD73 at specific epitopes.Type: GrantFiled: March 4, 2022Date of Patent: January 7, 2025Assignee: DEVELOPMENT CENTER FOR BIOTECHNOLOGYInventors: Chun-Chung Lee, Yu-Hsun Lo, Chu-Bin Liao, Chen-Jei Hong, Sih-Yu Chen, Yen-Yu Wu, Szu-Liang Lai, Chih-Yung Hu, Wen-Bin Ke, Ya-Ting Juan, Kao-Jean Huang
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Patent number: 12149211Abstract: A low noise amplifier (LNA) includes a pair of n-type transistors, each configured to provide a first transconductance; a pair of p-type transistors, each configured to provide a second transconductance; a first pair of coupling capacitors, cross-coupled between the pair of n-type transistors, and configured to provide a first boosting coefficient to the first transconductance; and a second pair of coupling capacitors, cross-coupled between the pair of p-type transistors, and configured to provide a second boosting coefficient to the second transconductance, wherein the LNA is configured to use a boosted effective transconductance based on the first and second boosting coefficients, and the first and second transconductances to amplify an input signal.Type: GrantFiled: August 8, 2022Date of Patent: November 19, 2024Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: An-Hsun Lo, Wen-Sheng Chen, En-Hsiang Yeh, Tzu-Jin Yeh
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Publication number: 20240209095Abstract: The present disclosure relates to an anti-PD-L1 antibody or an antigen-binding fragment thereof, comprising: a heavy chain variable region sequence comprising the three CDRs with the sequences of SEQ ID NOs: 2 to 4, or 6 to 8; and a light chain variable region sequence comprising the three CDRs with the sequences of SEQ ID NOs: 10 to 12, or 14 to 16. The present disclosure also relates to a pharmaceutical composition and a method for detecting expression of PD-L1 in a sample.Type: ApplicationFiled: November 29, 2023Publication date: June 27, 2024Applicant: DEVELOPMENT CENTER FOR BIOTECHNOLOGYInventors: SHU-PING YEH, CHENG-CHOU YU, YU-HSUN LO, JIN-YU WANG, MEI-CHI CHAN, CHAO-YANG HUANG, SZU-LIANG LAI
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Publication number: 20240197780Abstract: Disclosed herein is a chimeric antigen receptor (CAR) comprising a single-chain variable fragment specific to Globo H, a hinge and transmembrane domain, a co-stimulatory molecule, and a cytoplasmic domain. According to some embodiments of the present disclosure, the CAR further comprises a single-chain variable fragment specific to PD-L1, and optionally, a fragment crystallizable region of an immunoglobulin. Also disclosed herein are isolated nucleic acids encoding the CAR pharmaceutical kits comprising the isolated immune cells expressing the CAR, and methods of treating cancers by using isolated immune cells.Type: ApplicationFiled: December 18, 2023Publication date: June 20, 2024Inventors: Li-Shuang AI, Yu-Hsun LO, Cheng-Chou YU, Yi-Jiue TSAI, Hsin-Yi TSAI, Show-Shan SHEU, Yi-Tian HE, Pei-Yi TSAI, Chia-Tsen LAI
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Publication number: 20230279139Abstract: The present invention relates to a novel antibody, an antigen-binding fragment thereof and the uses of the antibody and fragment, wherein the antibody and the fragment comprise specific complementarity-determining regions (CDRs) and/or specifically bind to human CD73 at specific epitopes.Type: ApplicationFiled: March 4, 2022Publication date: September 7, 2023Inventors: Chun-Chung LEE, Yu-Hsun LO, Chu-Bin LIAO, Chen-Jei HONG, Sih-Yu CHEN, Yen-Yu WU, Szu-Liang LAI, Chih-Yung HU, Wen-Bin KE, Ya-Ting JUAN, Kao-Jean HUANG
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Publication number: 20230127322Abstract: A semiconductor device includes: a polygonal inductive device disposed on a first layer on a substrate, the polygonal inductive device including a first line portion; a first conductive line disposed on a second layer on the substrate; a second conductive line disposed on a third layer on the substrate; and a first conductive via arranged to electrically couple the second conductive line to the first conductive line; wherein the first layer is different from the second layer and the third layer, the first conductive line is electrically connected to a reference voltage, and the first conductive line crosses the first line portion viewing from a top of the semiconductor device.Type: ApplicationFiled: December 21, 2022Publication date: April 27, 2023Inventors: WEN-SHENG CHEN, AN-HSUN LO, EN-HSIANG YEH, TZU-JIN YEH
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Patent number: 11569164Abstract: A semiconductor device includes: a polygonal inductive device disposed on a first layer on a substrate, the polygonal inductive device including a first line portion; a first conductive line disposed on a second layer on the substrate; a second conductive line disposed on a third layer on the substrate; and a first conductive via arranged to electrically couple the second conductive line to the first conductive line; wherein the first layer is different from the second layer and the third layer, the first conductive line is electrically connected to a reference voltage, and the first conductive line crosses the first line portion viewing from a top of the semiconductor device.Type: GrantFiled: May 21, 2020Date of Patent: January 31, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.Inventors: Wen-Sheng Chen, An-Hsun Lo, En-Hsiang Yeh, Tzu-Jin Yeh
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Publication number: 20220385251Abstract: A low noise amplifier (LNA) includes a pair of n-type transistors, each configured to provide a first transconductance; a pair of p-type transistors, each configured to provide a second transconductance; a first pair of coupling capacitors, cross-coupled between the pair of n-type transistors, and configured to provide a first boosting coefficient to the first transconductance; and a second pair of coupling capacitors, cross-coupled between the pair of p-type transistors, and configured to provide a second boosting coefficient to the second transconductance, wherein the LNA is configured to use a boosted effective transconductance based on the first and second boosting coefficients, and the first and second transconductances to amplify an input signal.Type: ApplicationFiled: August 8, 2022Publication date: December 1, 2022Inventors: An-Hsun LO, Wen-Sheng CHEN, En-Hsiang YEH, Tzu-Jin YEH
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Patent number: 11456710Abstract: A low noise amplifier (LNA) includes a pair of n-type transistors, each configured to provide a first transconductance; a pair of p-type transistors, each configured to provide a second transconductance; a first pair of coupling capacitors, cross-coupled between the pair of n-type transistors, and configured to provide a first boosting coefficient to the first transconductance; and a second pair of coupling capacitors, cross-coupled between the pair of p-type transistors, and configured to provide a second boosting coefficient to the second transconductance, wherein the LNA is configured to use a boosted effective transconductance based on the first and second boosting coefficients, and the first and second transconductances to amplify an input signal.Type: GrantFiled: October 5, 2020Date of Patent: September 27, 2022Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: An-Hsun Lo, Wen-Sheng Chen, En-Hsiang Yeh, Tzu-Jin Yeh
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Patent number: 10985618Abstract: A wireless transmitter includes a an amplifier; and a switchable transformer, coupled to the amplifier, wherein the amplifier is configured to be coupled to the switchable transformer in first and second configurations, wherein the first configuration causes the amplifier to provide a first output impedance to the switchable transformer, and wherein the second configuration causes the amplifier to provide a second output impedance to the switchable transformer, the first and second output impedances being different from each other.Type: GrantFiled: October 28, 2019Date of Patent: April 20, 2021Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Wen-Sheng Chen, An-Hsun Lo, En-Hsiang Yeh, Tzu-Jin Yeh
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Publication number: 20210021240Abstract: A low noise amplifier (LNA) includes a pair of n-type transistors, each configured to provide a first transconductance; a pair of p-type transistors, each configured to provide a second transconductance; a first pair of coupling capacitors, cross-coupled between the pair of n-type transistors, and configured to provide a first boosting coefficient to the first transconductance; and a second pair of coupling capacitors, cross-coupled between the pair of p-type transistors, and configured to provide a second boosting coefficient to the second transconductance, wherein the LNA is configured to use a boosted effective transconductance based on the first and second boosting coefficients, and the first and second transconductances to amplify an input signal.Type: ApplicationFiled: October 5, 2020Publication date: January 21, 2021Inventors: An-Hsun LO, Wen-Sheng Chen, En-Hsiang Yeh, Tzu-Jin Yeh
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Patent number: 10797655Abstract: A low noise amplifier (LNA) includes a pair of n-type transistors, each configured to provide a first transconductance; a pair of p-type transistors, each configured to provide a second transconductance; a first pair of coupling capacitors, cross-coupled between the pair of n-type transistors, and configured to provide a first boosting coefficient to the first transconductance; and a second pair of coupling capacitors, cross-coupled between the pair of p-type transistors, and configured to provide a second boosting coefficient to the second transconductance, wherein the LNA is configured to use a boosted effective transconductance based on the first and second boosting coefficients, and the first and second transconductances to amplify an input signal.Type: GrantFiled: November 4, 2016Date of Patent: October 6, 2020Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: An-Hsun Lo, Wen-Sheng Chen, En-Hsiang Yeh, Tzu-Jin Yeh
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Publication number: 20200279808Abstract: A semiconductor device includes: a polygonal inductive device disposed on a first layer on a substrate, the polygonal inductive device including a first line portion; a first conductive line disposed on a second layer on the substrate; a second conductive line disposed on a third layer on the substrate; and a first conductive via arranged to electrically couple the second conductive line to the first conductive line; wherein the first layer is different from the second layer and the third layer, the first conductive line is electrically connected to a reference voltage, and the first conductive line crosses the first line portion viewing from a top of the semiconductor device.Type: ApplicationFiled: May 21, 2020Publication date: September 3, 2020Inventors: WEN-SHENG CHEN, AN-HSUN LO, EN-HSIANG YEH, TZU-JIN YEH
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Patent number: 10672704Abstract: A semiconductor device includes: a polygonal inductive device disposed on a first layer on a substrate, the polygonal inductive device including a first line portion; a first conductive line disposed on a second layer on the substrate; a second conductive line disposed on a third layer on the substrate; and a first conductive via arranged to electrically couple the second conductive line to the first conductive line; wherein the first layer is different from the second layer and the third layer, the first conductive line is electrically connected to a reference voltage, and the first conductive line crosses the first line portion viewing from a top of the semiconductor device.Type: GrantFiled: April 27, 2018Date of Patent: June 2, 2020Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.Inventors: Wen-Sheng Chen, An-Hsun Lo, En-Hsiang Yeh, Tzu-Jin Yeh
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Patent number: 10644996Abstract: A route determining method and apparatus, and a communications device are provided. The method includes: obtaining startpoint information and endpoint information of a required path, where the startpoint information includes a sequence number of a startpoint POD and a sequence number of a startpoint edge switch, and the endpoint information includes a sequence number of an endpoint POD and a sequence number of an endpoint edge switch; determining, from an n-dimensional Latin square, an element whose row is the sequence number of the startpoint edge switch and column is the sequence number of the endpoint edge switch; and if the sequence number of the startpoint POD is the same as the sequence number of the endpoint POD, determining that the required path is the startpoint edge switch, an aggregation switch corresponding to the element in the POD, and the endpoint edge switch.Type: GrantFiled: January 17, 2019Date of Patent: May 5, 2020Assignee: HUAWEI TECHNOLOGIES CO., LTD.Inventors: Yuan-Hsun Lo, Wing Shing Wong, Yong Huang
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Publication number: 20200067351Abstract: A wireless transmitter includes a an amplifier; and a switchable transformer, coupled to the amplifier, wherein the amplifier is configured to be coupled to the switchable transformer in first and second configurations, wherein the first configuration causes the amplifier to provide a first output impedance to the switchable transformer, and wherein the second configuration causes the amplifier to provide a second output impedance to the switchable transformer, the first and second output impedances being different from each other.Type: ApplicationFiled: October 28, 2019Publication date: February 27, 2020Inventors: Wen-Sheng Chen, An-Hsun Lo, En-Hsiang Yeh, Tzu-Jin Yeh
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Patent number: 10491046Abstract: A wireless transmitter includes a an amplifier; and a switchable transformer, coupled to the amplifier, wherein the amplifier is configured to be coupled to the switchable transformer in first and second configurations, wherein the first configuration causes the amplifier to provide a first output impedance to the switchable transformer, and wherein the second configuration causes the amplifier to provide a second output impedance to the switchable transformer, the first and second output impedances being different from each other.Type: GrantFiled: October 20, 2016Date of Patent: November 26, 2019Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Wen-Sheng Chen, An-Hsun Lo, En-Hsiang Yeh, Tzu-Jin Yeh
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Publication number: 20190164886Abstract: A semiconductor device includes: a polygonal inductive device disposed on a first layer on a substrate, the polygonal inductive device including a first line portion; a first conductive line disposed on a second layer on the substrate; a second conductive line disposed on a third layer on the substrate; and a first conductive via arranged to electrically couple the second conductive line to the first conductive line; wherein the first layer is different from the second layer and the third layer, the first conductive line is electrically connected to a reference voltage, and the first conductive line crosses the first line portion viewing from a top of the semiconductor device.Type: ApplicationFiled: April 27, 2018Publication date: May 30, 2019Inventors: WEN-SHENG CHEN, AN-HSUN LO, EN-HSIANG YEH, TZU-JIN YEH