Patents by Inventor An-Hwa Chang
An-Hwa Chang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 12220377Abstract: The present invention provides a portable guidance device for cardiopulmonary resuscitation, which comprises a tri-axial gravity sensing element, a pressure sensing element, a sound output element, a visual output element and a microcontroller. The portable guidance device for cardiopulmonary resuscitation can actively connect to the medical rescue system and issue an alarm to guide the surrounding passers-by to perform real-time rescue and perform correct cardiopulmonary resuscitation, so as to improve the efficiency and accuracy of chest compressions.Type: GrantFiled: December 13, 2019Date of Patent: February 11, 2025Assignees: NATIONAL TAIWAN UNIVERSITY HOSPITAL, FINE-I LTD.Inventors: Ting An Yen, Ching Chia Wang, Hwa Chang Wang
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Publication number: 20250022015Abstract: An operation method of an application system includes receiving a chat room-entry event notifying that a user enters the chat room from a terminal in which an application is installed, generating an entry trigger based on the chat room enter event, and providing user context suitable information inferred based on a user key included in the entry trigger to the chat room.Type: ApplicationFiled: September 27, 2024Publication date: January 16, 2025Inventors: YOUNG JIN HUH, SUNG YONG CHANG, SOOK YOUNG LEE, Jisoo HWANG, Hye Ryeon LEE, SEON HWA KIM, YOUNGHAE LEE, JIN HWAN KIM
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Publication number: 20250006686Abstract: A semiconductor device includes a low-density substrate, a high-density patch positioned inside a cavity in the low-density substrate, a first semiconductor die, and a second semiconductor die. The first semiconductor dies includes high-density bumps and low-density bumps. The second semiconductor die includes high-density bumps and low-density bumps. The high-density bumps of the first semiconductor die and the high-density bumps of the second semiconductor die are electrically connected to the high-density patch. The low-density bumps of the first semiconductor die and the low-density bumps of the second semiconductor die are electrically connected to the low-density substrate.Type: ApplicationFiled: July 8, 2024Publication date: January 2, 2025Inventors: Jae Hun Bae, Won Chul Do, Min Yoo, Young Rae Kim, Min Hwa Chang, Dong Hyun Kim, Ah Ra Jo, Seok Geun Ahn
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Patent number: 12116662Abstract: A process enables growing thick stoichiometric crystalline and preferably IR-transparent optical PCMO material on Si and other substrates. Sputter deposition is carried out in oxygen-free inert gas (e.g., Ar) environment, which helps to prevent decomposition of the PCMO material over the substrate. In the disclosed process, there is no need to add a seed layer prior to PCMO deposition. Moreover, no post-deposition annealing is needed in a high-temperature and high-pressure oxygen furnace, but an anneal provides certain additional benefits in terms of improved transparency at IR wavelengths. Over a long deposition time for a thick PCMO film on the high temperature (?450° C.) substrates, the PCMO deposition is made repeated cycles of deposition of the PCMO material at the high temperature, each deposition cycle being followed by cooling the PCMO-deposited substrate to a substantially lower temperature (<50° C.).Type: GrantFiled: August 18, 2022Date of Patent: October 15, 2024Assignee: HRL LABORATORIES, LLCInventors: Kyung-Ah Son, Jeong-Sun Moon, Hwa Chang Seo, Richard M. Kremer, Ryan G. Quarfoth, Jack A. Crowell, Mariano J. Taboada, Joshua M. Doria, Terry B. Welch
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Publication number: 20240258182Abstract: In one example, a semiconductor device can comprise a substrate, a device stack, first and second internal interconnects, and an encapsulant. The substrate can comprise a first and second substrate sides opposite each other, a substrate outer sidewall between the first substrate side and the second substrate side, and a substrate inner sidewall defining a cavity between the first substrate side and the second substrate side. The device stack can be in the cavity and can comprise a first electronic device, and a second electronic device stacked on the first electronic device. The first internal interconnect can be coupled to the substrate and the device stack. The encapsulant can cover the substrate inner sidewall and the device stack and can fill the cavity. Other examples and related methods are disclosed herein.Type: ApplicationFiled: April 12, 2024Publication date: August 1, 2024Applicant: Amkor Technology Singapore Holding Pte. Ltd.Inventors: Gyu Wan Han, Won Bae Bang, Ju Hyung Lee, Min Hwa Chang, Dong Joo Park, Jin Young Khim, Jae Yun Kim, Se Hwan Hong, Seung Jae Yu, Shaun Bowers, Gi Tae Lim, Byoung Woo Cho, Myung Jea Choi, Seul Bee Lee, Sang Goo Kang, Kyung Rok Park
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Publication number: 20240238777Abstract: Provided herein is a kit for isolation of platelet-rich plasma, comprising a first isolation tube and a second isolation tube. The first isolation tube comprises a first opening and a second opening, and the second isolation tube comprises a first portion, a second portion, and a filter, wherein the first portion has a third opening, the filter is disposed between the first portion and the second portion, the second opening has a diameter in a range of 1 to 5 mm and the filter has a pore size in a range of 1.5 to 4 ?m.Type: ApplicationFiled: February 9, 2024Publication date: July 18, 2024Applicant: KARTIGEN BIOMEDICAL INC.Inventors: Hwa-Chang LIU, Feng-Huei LIN, Chun-Che YEN
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Publication number: 20240234556Abstract: A transition metal dichalcogenide (TMD) transistor includes a substrate, an n-type two-dimensional (2D) TMD layer, a metal source electrode, a metal drain electrode, and a gate dielectric. The substrate has a top portion that is an insulating layer, and the n-type 2D TMD layer is on the insulating layer. The metal source electrode, the metal drain electrode, and the gate dielectric are on the n-type 2D TMD layer. The metal gate electrode is on top of the gate dielectric and is between the metal source electrode and the metal drain electrode.Type: ApplicationFiled: October 19, 2022Publication date: July 11, 2024Applicant: HRL Laboratories, LLCInventors: Kyung-Ah SON, Jeong-Sun MOON, Hwa Chang SEO
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Patent number: 12033970Abstract: A semiconductor device includes a low-density substrate, a high-density patch positioned inside a cavity in the low-density substrate, a first semiconductor die, and a second semiconductor die. The first semiconductor dies includes high-density bumps and low-density bumps. The second semiconductor die includes high-density bumps and low-density bumps. The high-density bumps of the first semiconductor die and the high-density bumps of the second semiconductor die are electrically connected to the high-density patch. The low-density bumps of the first semiconductor die and the low-density bumps of the second semiconductor die are electrically connected to the low-density substrate.Type: GrantFiled: May 24, 2021Date of Patent: July 9, 2024Assignee: AMKOR TECHNOLOGY SINGAPORE HOLDING PTE. LTD.Inventors: Jae Hun Bae, Won Chul Do, Min Yoo, Young Rae Kim, Min Hwa Chang, Dong Hyun Kim, Ah Ra Jo, Seok Geun Ahn
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Patent number: 11988907Abstract: An electric field-controlled refractive index tunable device includes a phase change correlated transition metal oxide layer, and E-field responsive charge dopants. The E-field responsive charge dopants either accumulate in the phase change correlated transition metal oxide layer or are depleted from the phase change correlated transition metal oxide layer in response to an E-field applied to the phase change correlated transition metal oxide layer.Type: GrantFiled: March 25, 2021Date of Patent: May 21, 2024Assignee: HRL LABORATORIES, LLCInventors: Kyung-Ah Son, Jeong-Sun Moon, Hwa Chang Seo, Richard M. Kremer, Ryan G. Quarfoth
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Publication number: 20240136429Abstract: A transition metal dichalcogenide (TMD) transistor includes a substrate, an n-type two-dimensional (2D) TMD layer, a metal source electrode, a metal drain electrode, and a gate dielectric. The substrate has a top portion that is an insulating layer, and the n-type 2D TMD layer is on the insulating layer. The metal source electrode, the metal drain electrode, and the gate dielectric are on the n-type 2D TMD layer. The metal gate electrode is on top of the gate dielectric and is between the metal source electrode and the metal drain electrode.Type: ApplicationFiled: October 18, 2022Publication date: April 25, 2024Applicant: HRL Laboratories, LLCInventors: Kyung-Ah SON, Jeong-Sun MOON, Hwa Chang SEO
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Patent number: 11961775Abstract: In one example, a semiconductor device can comprise a substrate, a device stack, first and second internal interconnects, and an encapsulant. The substrate can comprise a first and second substrate sides opposite each other, a substrate outer sidewall between the first substrate side and the second substrate side, and a substrate inner sidewall defining a cavity between the first substrate side and the second substrate side. The device stack can be in the cavity and can comprise a first electronic device, and a second electronic device stacked on the first electronic device. The first internal interconnect can be coupled to the substrate and the device stack. The encapsulant can cover the substrate inner sidewall and the device stack and can fill the cavity. Other examples and related methods are disclosed herein.Type: GrantFiled: November 8, 2022Date of Patent: April 16, 2024Assignee: Amkor Technology Singapore Holding Pte. Ltd.Inventors: Gyu Wan Han, Won Bae Bang, Ju Hyung Lee, Min Hwa Chang, Dong Joo Park, Jin Young Khim, Jae Yun Kim, Se Hwan Hong, Seung Jae Yu, Shaun Bowers, Gi Tae Lim, Byoung Woo Cho, Myung Jea Choi, Seul Bee Lee, Sang Goo Kang, Kyung Rok Park
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Patent number: 11808937Abstract: A method of providing a spatial light modulator comprising: providing a substrate; providing a first phase change material cell on the substrate, the first phase change material cell comprising: a first electrical heater on the substrate; a first optical reflector layer on the electrical heater; and a first phase change material layer on the optical reflector layer; and providing at least a second phase change material cell on the substrate, the second phase change material cell comprising: a second electrical heater on the substrate; a second optical reflector layer on the second electrical heater; a second phase change material layer on the second optical reflector layer; and providing a light absorber layer between the first phase change material cell and the second phase change material cell.Type: GrantFiled: October 27, 2021Date of Patent: November 7, 2023Assignee: HRL LABORATORIES, LLCInventors: Jeong-Sun Moon, Hwa Chang Seo, Kyung-Ah Son, Kangmu Lee
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Patent number: 11788183Abstract: A process enables growing thick stoichiometric crystalline and preferably IR-transparent optical PCMO material on Si and other substrates. Sputter deposition is carried out in oxygen-free inert gas (e.g., Ar) environment, which helps to prevent decomposition of the PCMO material over the substrate. In the disclosed process, there is no need to add a seed layer prior to PCMO deposition. Moreover, no post-deposition annealing is needed in a high-temperature and high-pressure oxygen furnace, but an anneal provides certain additional benefits in terms of improved transparency at IR wavelengths. Over a long deposition time for a thick PCMO film on the high temperature (?450° C.) substrates, the PCMO deposition is made repeated cycles of deposition of the PCMO material at the high temperature, each deposition cycle being followed by cooling the PCMO-deposited substrate to a substantially lower temperature (<50° C.).Type: GrantFiled: March 19, 2021Date of Patent: October 17, 2023Assignee: HRL LABORATORIES, LLCInventors: Kyung-Ah Son, Jeong-Sun Moon, Hwa Chang Seo, Richard M. Kremer, Ryan G. Quarfoth, Jack A. Crowell, Mariano J. Taboada, Joshua M. Doria, Terry B. Welch
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Publication number: 20230070922Abstract: In one example, a semiconductor device can comprise a substrate, a device stack, first and second internal interconnects, and an encapsulant. The substrate can comprise a first and second substrate sides opposite each other, a substrate outer sidewall between the first substrate side and the second substrate side, and a substrate inner sidewall defining a cavity between the first substrate side and the second substrate side. The device stack can be in the cavity and can comprise a first electronic device, and a second electronic device stacked on the first electronic device. The first internal interconnect can be coupled to the substrate and the device stack. The encapsulant can cover the substrate inner sidewall and the device stack and can fill the cavity. Other examples and related methods are disclosed herein.Type: ApplicationFiled: November 8, 2022Publication date: March 9, 2023Applicant: Amkor Technology Singapore Holding Pte. Ltd.Inventors: Gyu Wan Han, Won Bae Bang, Ju Hyung Lee, Min Hwa Chang, Dong Joo Park, Jin Young Khim, Jae Yun Kim, Se Hwan Hong, Seung Jae Yu, Shaun Bowers, Gi Tae Lim, Byoung Woo Cho, Myung Jea Choi, Seul Bee Lee, Sang Goo Kang, Kyung Rok Park
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Patent number: 11569367Abstract: A field effect transistor includes a substrate, a passivation layer on the substrate forming a passivated substrate, wherein the passivation layer is inert to XeF2, and a graphene lateral heterostructure field effect transistor (LHFET) on the passivated substrate.Type: GrantFiled: April 27, 2021Date of Patent: January 31, 2023Assignee: HRL LABORATORIES, LLCInventors: Kyung-Ah Son, Jeong-Sun Moon, Hwa Chang Seo
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Patent number: 11549072Abstract: The invention relates to an improved system and method for relief of hot, high pressure, fouling fluid from the 1st Stage Reactor and the ISS in case of an unintended overpressure situation while allowing the quick establishing of normal fluid flow path once the overpressure situation has been corrected. This allows for rapid cooling of all subsequent reactor stages while minimizing VGO slop generation that needs reprocessing.Type: GrantFiled: September 13, 2021Date of Patent: January 10, 2023Assignee: AxensInventors: Trushit Oza, Yu-Hwa Chang
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Publication number: 20220389561Abstract: A process enables growing thick stoichiometric crystalline and preferably IR-transparent optical PCMO material on Si and other substrates. Sputter deposition is carried out in oxygen-free inert gas (e.g., Ar) environment, which helps to prevent decomposition of the PCMO material over the substrate. In the disclosed process, there is no need to add a seed layer prior to PCMO deposition. Moreover, no post-deposition annealing is needed in a high-temperature and high-pressure oxygen furnace, but an anneal provides certain additional benefits in terms of improved transparency at IR wavelengths. Over a long deposition time for a thick PCMO film on the high temperature (?450° C.) substrates, the PCMO deposition is made repeated cycles of deposition of the PCMO material at the high temperature, each deposition cycle being followed by cooling the PCMO-deposited substrate to a substantially lower temperature (<50° C.).Type: ApplicationFiled: August 18, 2022Publication date: December 8, 2022Applicant: HRL Laboratories, LLCInventors: Kyung-Ah SON, Jeong-Sun MOON, Hwa Chang SEO, Richard M. KREMER, Ryan G. QUARFOTH, Jack A. CROWELL, Mariano J. TABOADA, Joshua M. DORIA, Terry B. WELCH
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Patent number: 11495505Abstract: In one example, a semiconductor device can comprise a substrate, a device stack, first and second internal interconnects, and an encapsulant. The substrate can comprise a first and second substrate sides opposite each other, a substrate outer sidewall between the first substrate side and the second substrate side, and a substrate inner sidewall defining a cavity between the first substrate side and the second substrate side. The device stack can be in the cavity and can comprise a first electronic device, and a second electronic device stacked on the first electronic device. The first internal interconnect can be coupled to the substrate and the device stack. The encapsulant can cover the substrate inner sidewall and the device stack and can fill the cavity. Other examples and related methods are disclosed herein.Type: GrantFiled: September 11, 2020Date of Patent: November 8, 2022Assignee: Amkor Technology Singapore Holding Pte. Ltd.Inventors: Gyu Wan Han, Won Bae Bang, Ju Hyung Lee, Min Hwa Chang, Dong Joo Park, Jin Young Khim, Jae Yun Kim, Se Hwan Hong, Seung Jae Yu, Shaun Bowers, Gi Tae Lim, Byoung Woo Cho, Myung Jea Choi, Seul Bee Lee, Sang Goo Kang, Kyung Rok Park
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Publication number: 20220352129Abstract: In one example, a semiconductor structure comprises a frontside substrate comprising a conductive structure, a backside substrate comprising a base substrate and a cavity substrate contacting the base substrate, wherein the backside substrate is over a top side of the frontside substrate and has a cavity and an internal interconnect contacting the frontside substrate, and a first electronic component over the top side of the frontside substrate and in the cavity. The first electronic component is coupled with the conductive structure, and an encapsulant is in the cavity and on the top side of the frontside substrate, contacting a lateral side of the first electronic component, a lateral side of the cavity, and a lateral side of the internal interconnect. Other examples and related methods are also disclosed herein.Type: ApplicationFiled: July 14, 2022Publication date: November 3, 2022Applicant: Amkor Technology Singapore Holding Pte. Ltd.Inventors: Gi Tae Lim, Jae Yun Kim, Myung Jae Choi, Min Hwa Chang, Mi Kyoung Choi
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Patent number: 11398455Abstract: In one example, a semiconductor device can comprise a substrate, a device stack, first and second internal interconnects, and an encapsulant. The substrate can comprise a first and second substrate sides opposite each other, a substrate outer sidewall between the first substrate side and the second substrate side, and a substrate inner sidewall defining a cavity between the first substrate side and the second substrate side. The device stack can be in the cavity and can comprise a first electronic device, and a second electronic device stacked on the first electronic device. The first internal interconnect can be coupled to the substrate and the device stack. The second internal interconnect can be coupled to the second electronic device and the first electronic device. The encapsulant can cover the substrate inner sidewall and the device stack, and can fill the cavity. Other examples and related methods are disclosed herein.Type: GrantFiled: June 3, 2019Date of Patent: July 26, 2022Assignee: Amkor Technology Singapore Holding Pte. Ltd.Inventors: Gyu Wan Han, Won Bae Bang, Ju Hyung Lee, Min Hwa Chang, Dong Joo Park, Jin Young Khim, Jae Yun Kim, Se Hwan Hong, Seung Jae Yu, Shaun Bowers, Gi Tae Lim, Byoung Woo Cho, Myung Jea Choi, Seul Bee Lee