Patents by Inventor An-Jiao FU
An-Jiao FU has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20230335499Abstract: Some embodiments relate to a semiconductor structure including a dielectric layer over a substrate. A conductive body is disposed within the dielectric layer. The conductive body has a bottom surface continuously extending between opposing sidewalls. A first liner layer is disposed between the conductive body and the dielectric layer. The first liner layer extends along the opposing sidewalls of the conductive body. The first liner layer is laterally offset from a central region of the bottom surface of the conductive body by a non-zero distance.Type: ApplicationFiled: June 28, 2023Publication date: October 19, 2023Inventors: Hsiu-Wen Hsueh, Chii-Ping Chen, Neng-Jye Yang, Ya-Lien Lee, An-Jiao Fu, Ya-Ching Tseng
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Patent number: 11742291Abstract: Some embodiments relate to a semiconductor structure including a method for forming a semiconductor structure. The method includes forming a lower conductive structure within a first dielectric layer over a substrate. An upper dielectric structure is formed over the lower conductive structure. The upper dielectric structure comprises sidewalls defining an opening over the lower conductive structure. A first liner layer is selectively deposited along the sidewalls of the upper dielectric structure. A conductive body is formed within the opening and over the lower conductive structure. The conductive body has a bottom surface directly overlying a middle region of the lower conductive structure. The first layer is laterally offset from the middle region of the lower conductive structure by a non-zero distance.Type: GrantFiled: June 7, 2022Date of Patent: August 29, 2023Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Hsiu-Wen Hsueh, Chii-Ping Chen, Neng-Jye Yang, Ya-Lien Lee, An-Jiao Fu, Ya-Ching Tseng
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Publication number: 20230215804Abstract: A method of making a semiconductor device includes electrically connecting a component to a first side of a first fuse, wherein the first fuse is a first distance from the component. The method further includes electrically connecting the component to a first side of a second fuse, wherein the second fuse is a second distance from the component, and the second distance is different than the first distance. The method further includes electrically connecting a second side of the second fuse to a dummy vertical interconnect segment.Type: ApplicationFiled: March 13, 2023Publication date: July 6, 2023Inventors: Meng-Sheng CHANG, Shao-Yu CHOU, Po-Hsiang HUANG, An-Jiao FU, Chih-Hao CHEN
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Patent number: 11626368Abstract: A method of making a semiconductor device includes operations directed toward electrically connecting a component to a first fuse, wherein the first fuse is on a first conductive level a first distance from the component; identifying a conductive element for omission between the first fuse and a second fuse; and electrically connecting the component to the second fuse, wherein the second fuse is on a second conductive level a second distance from the component, the second distance is greater than the first distance, and the electrically connecting the component to the second fuse comprises electrically connecting the component to the second fuse without forming the identified conductive element.Type: GrantFiled: January 28, 2022Date of Patent: April 11, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Meng-Sheng Chang, Shao-Yu Chou, Po-Hsiang Huang, An-Jiao Fu, Chih-Hao Chen
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Publication number: 20220375859Abstract: In the present disclosure, a semiconductor structure includes an Mx-1 layer including a first dielectric layer and first metal features, wherein the first metal features include a first set of first metal features in a first region and a second set of first metal features in a second region, wherein the first set has a first pattern density and the second set has a second pattern density being greater than the first pattern density. The structure further includes a Vx layer disposed over the Mx-1 layer, the Vx layer including first vias contacting the first set of the first metal features. The structure further includes an Mx layer disposed over the Vx layer, the Mx layer including a fuse element, wherein the fuse element has a first thickness in the first region less than a second thickness in the second region.Type: ApplicationFiled: July 27, 2022Publication date: November 24, 2022Inventors: An-Jiao Fu, Po-Hsiang Huang, Derek Hsu, Hsiu-Wen Hsueh, Meng-Sheng Chang
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Publication number: 20220310526Abstract: Some embodiments relate to a semiconductor structure including a method for forming a semiconductor structure. The method includes forming a lower conductive structure within a first dielectric layer over a substrate. An upper dielectric structure is formed over the lower conductive structure. The upper dielectric structure comprises sidewalls defining an opening over the lower conductive structure. A first liner layer is selectively deposited along the sidewalls of the upper dielectric structure. A conductive body is formed within the opening and over the lower conductive structure. The conductive body has a bottom surface directly overlying a middle region of the lower conductive structure. The first layer is laterally offset from the middle region of the lower conductive structure by a non-zero distance.Type: ApplicationFiled: June 7, 2022Publication date: September 29, 2022Inventors: Hsiu-Wen Hsueh, Chii-Ping Chen, Neng-Jye Yang, Ya-Lien Lee, An-Jiao Fu, Ya-Ching Tseng
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Patent number: 11410926Abstract: In the present disclosure, a semiconductor structure includes an Mx-1 layer including a first dielectric layer and first metal features, wherein the first metal features include a first set of first metal features in a first region and a second set of first metal features in a second region, wherein the first set has a first pattern density and the second set has a second pattern density being greater than the first pattern density. The structure further includes a Vx layer disposed over the Mx-1 layer, the Vx layer including first vias contacting the first set of the first metal features. The structure further includes an Mx layer disposed over the Vx layer, the Mx layer including a fuse element, wherein the fuse element has a first thickness in the first region less than a second thickness in the second region.Type: GrantFiled: July 24, 2020Date of Patent: August 9, 2022Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: An-Jiao Fu, Po-Hsiang Huang, Derek Hsu, Hsiu-Wen Hsueh, Meng-Sheng Chang
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Patent number: 11362035Abstract: Some embodiments relate to a semiconductor structure including a first inter-level dielectric (ILD) layer overlying a substrate. A lower conductive structure is disposed within the first ILD layer. A capping layer continuously extends along a top surface of the lower conductive structure. An upper ILD structure overlies the lower conductive structure. A conductive body is disposed within the upper ILD structure. A bottom surface of the conductive body directly overlies the top surface of the lower conductive structure. A width of the bottom surface of the conductive body is less than a width of the top surface of the lower conductive structure. A diffusion barrier layer is disposed between the conductive body and the upper ILD structure. The diffusion barrier layer is laterally offset from a region disposed directly between the bottom surface of the conductive body and the top surface of the lower conductive structure by a non-zero distance.Type: GrantFiled: March 10, 2020Date of Patent: June 14, 2022Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Hsiu-Wen Hsueh, Chii-Ping Chen, Neng-Jye Yang, Ya-Lien Lee, An-Jiao Fu, Ya-Ching Tseng
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Publication number: 20220157718Abstract: A method of making a semiconductor device includes operations directed toward electrically connecting a component to a first fuse, wherein the first fuse is on a first conductive level a first distance from the component; identifying a conductive element for omission between the first fuse and a second fuse; and electrically connecting the component to the second fuse, wherein the second fuse is on a second conductive level a second distance from the component, the second distance is greater than the first distance, and the electrically connecting the component to the second fuse comprises electrically connecting the component to the second fuse without forming the identified conductive element.Type: ApplicationFiled: January 28, 2022Publication date: May 19, 2022Inventors: Meng-Sheng CHANG, Shao-Yu CHOU, Po-Hsiang HUANG, An-Jiao FU, Chih-Hao CHEN
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Patent number: 11257757Abstract: A semiconductor device includes a component having a functionality. The semiconductor device further includes an interconnect structure electrically connected to the component. The interconnect structure is configured to electrically connect the component to a signal. The interconnect structure includes a first column of conductive elements and a second column of conductive elements. The interconnect structure further includes a first fuse on a first conductive level a first distance from the component, wherein the first fuse electrically connects the first column of conductive elements to the second column of conductive elements. The interconnect structure further includes a second fuse on a second conductive level a second distance from the component, wherein the second fuse electrically connects the first column of conductive elements to the second column of conductive elements, and the second distance is different from the first distance.Type: GrantFiled: September 17, 2019Date of Patent: February 22, 2022Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Meng-Sheng Chang, Shao-Yu Chou, Po-Hsiang Huang, An-Jiao Fu, Chih-Hao Chen
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Publication number: 20210287994Abstract: Some embodiments relate to a semiconductor structure including a first inter-level dielectric (ILD) layer overlying a substrate. A lower conductive structure is disposed within the first ILD layer. A capping layer continuously extends along a top surface of the lower conductive structure. An upper ILD structure overlies the lower conductive structure. A conductive body is disposed within the upper ILD structure. A bottom surface of the conductive body directly overlies the top surface of the lower conductive structure. A width of the bottom surface of the conductive body is less than a width of the top surface of the lower conductive structure. A diffusion barrier layer is disposed between the conductive body and the upper ILD structure. The diffusion barrier layer is laterally offset from a region disposed directly between the bottom surface of the conductive body and the top surface of the lower conductive structure by a non-zero distance.Type: ApplicationFiled: March 10, 2020Publication date: September 16, 2021Inventors: Hsiu-Wen Hsueh, Chii-Ping Chen, Neng-Jye Yang, Ya-Lien Lee, An-Jiao Fu, Ya-Ching Tseng
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Publication number: 20210098372Abstract: In the present disclosure, a semiconductor structure includes an Mx-1 layer including a first dielectric layer and first metal features, wherein the first metal features include a first set of first metal features in a first region and a second set of first metal features in a second region, wherein the first set has a first pattern density and the second set has a second pattern density being greater than the first pattern density. The structure further includes a Vx layer disposed over the Mx-1 layer, the Vx layer including first vias contacting the first set of the first metal features. The structure further includes an Mx layer disposed over the Vx layer, the Mx layer including a fuse element, wherein the fuse element has a first thickness in the first region less than a second thickness in the second region.Type: ApplicationFiled: July 24, 2020Publication date: April 1, 2021Inventors: An-Jiao Fu, Po-Hsiang Huang, Derek Hsu, Hsiu-Wen Hsueh, Meng-Sheng Chang
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Publication number: 20210082812Abstract: A semiconductor device includes a component having a functionality. The semiconductor device further includes an interconnect structure electrically connected to the component. The interconnect structure is configured to electrically connect the component to a signal. The interconnect structure includes a first column of conductive elements and a second column of conductive elements. The interconnect structure further includes a first fuse on a first conductive level a first distance from the component, wherein the first fuse electrically connects the first column of conductive elements to the second column of conductive elements. The interconnect structure further includes a second fuse on a second conductive level a second distance from the component, wherein the second fuse electrically connects the first column of conductive elements to the second column of conductive elements, and the second distance is different from the first distance.Type: ApplicationFiled: September 17, 2019Publication date: March 18, 2021Inventors: Meng-Sheng CHANG, Shao-Yu CHOU, Po-Hsiang HUANG, An-Jiao FU, Chih-Hao CHEN
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Patent number: D903376Type: GrantFiled: May 29, 2019Date of Patent: December 1, 2020Assignee: Chengdu Jiechen Technology Ltd. Co.Inventor: Jiao Jiao Fu