Patents by Inventor An-Ju LIN

An-Ju LIN has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250149426
    Abstract: A package structure includes a package substrate, an organic interposer and an electronic unit. The package substrate includes a plurality of first pads. The organic interposer is disposed on the package substrate and includes a plurality of second pads. The second pads are directly connected to the first pads to electrically connected the organic interposer to the package substrate. At least one of each of the first pads and each of the second pads includes a pad portion and a plurality of contact portions connecting the pad portion. A first extension direction of the pad portion is different from a second extension direction of the contact portions. The electronic unit is disposed on the organic interposer, wherein the electronic unit is electrically connected to the package substrate through the organic interposer.
    Type: Application
    Filed: September 24, 2024
    Publication date: May 8, 2025
    Applicant: Unimicron Technology Corp.
    Inventors: An-Sheng Lee, Chen-Hao Lin, Kai-Ming Yang, Pu-Ju Lin, Cheng-Ta Ko, Chin-Sheng Wang, Tzyy-Jang Tseng
  • Publication number: 20250136869
    Abstract: Liquid Crystal Elastomer (LCE) fibers, an apparatus for manufacturing, and a method for using the apparatus are provided. LCE fibers formed from each of a plurality of resin recipes can undergo reversible temperature driven actuation of the fiber. Each of the resin recipes forms a fiber having a different actuation temperature. The apparatus includes: an extrusion device, a drawing bobbin, a coating basin, a collector bobbin, a first plurality of curing devices, and a second plurality of curing devices, to transform a resin recipe into a LCE fiber. In operation, the extrusion device extrudes the resin through to the first plurality of curing devices for a partial cure. Once in contact with drawing bobbin the resin is coated in a fluid, and then pull through the second plurality of curing devices for a final cure by collector bobbin, where it can be collected and post-processed.
    Type: Application
    Filed: October 25, 2024
    Publication date: May 1, 2025
    Applicant: Massachusetts Institute of Technology
    Inventors: Jack Forman, Ozgun Kilic Afsar, Sarah Nicita, Rosalie Hsin-Ju Lin, Cedric Honnet, Neil Gershenfeld, Hiroshi Ishii
  • Publication number: 20250123456
    Abstract: An optical module, comprising a circuit board (110), a photoelectric assembly (130) electrically connected to the circuit board (110), an optical interface (120), and optical fiber (140) in optical communication with the photoelectric assembly (130) and the optical interface (120), and a fiber coiling member (150). The fiber coiling member (150) comprises a fiber coiling body (151) enclosing an accommodating cavity (1510), and the fiber coiling body (151) is provided with a bottom wall (1512) and a fiber coiling wall (1511) extending from the bottom wall (1512) in the thickness direction of the circuit board (110). The fiber coiling wall (1511) defines a peripheral boundary of the accommodating cavity (1510). The fiber coiling member (150) further comprises stop walls (152) arranged opposite to the bottom wall (1512) in the thickness direction of the circuit board (110), and protruding from the fiber coiling wall (1511) to the interior of the accommodating cavity (1510).
    Type: Application
    Filed: November 10, 2022
    Publication date: April 17, 2025
    Inventors: Yin Wei, Lan Yang, Xiu-Ling Deng, Peng Xiao, Ju-Lin Zhang, Qing Huang, Gang Chen
  • Patent number: 12275953
    Abstract: A method for screening host cells expressing a target protein is provided. The method includes the following steps: providing an expression vector, the expression vector including a promoter, a gene encoding a target protein and an FTH1 gene; transfecting the host cells with the expression vector; culturing the host cells in a medium; and adding iron ions to the medium, and screening the surviving host cells to obtain the host cells expressing the target protein. An expression vector and a method for establishing a cell line stably expressing an exogenous recombinant gene are also provided.
    Type: Grant
    Filed: December 29, 2021
    Date of Patent: April 15, 2025
    Assignee: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
    Inventors: Yen-Ju Lin, Mei-Wei Lin, Min-Yuan Chou
  • Publication number: 20250117887
    Abstract: An image processing method and an image processing apparatus for video conferencing are provided. In the method, one or more background areas in a shared screen are identified. Whether a size of the one or more background areas conforms to a size of a character representative image is determined. The character representative image is presented in a background area conforming to the size of the character representative image. Therefore, the complete briefing content can be seen.
    Type: Application
    Filed: November 14, 2023
    Publication date: April 10, 2025
    Applicant: Acer Incorporated
    Inventors: I-Yuan Hu, Ling-Fan Tsao, Yen-Ju Lin
  • Publication number: 20250119740
    Abstract: A connection authentication method is provided in the invention. The connection authentication method may comprise the following steps. A master device may provide a white list to a wireless network device, wherein the white list comprises white list information of at least one authorized device. Then, the wireless network device may connect to the at least one authorized device according to the white list to provide network connection to the at least one authorized device.
    Type: Application
    Filed: June 3, 2024
    Publication date: April 10, 2025
    Inventors: Sheng-Hsiung YAO, Ling-Fan TSAO, Yen-Ju LIN
  • Patent number: 12272621
    Abstract: The present disclosure describes a buried conductive structure in a semiconductor substrate and a method for forming the structure. The structure includes an epitaxial region disposed on a substrate and adjacent to a nanostructured gate layer and a nanostructured channel layer, a first silicide layer disposed within a top portion of the epitaxial region, and a first conductive structure disposed on a top surface of the first silicide layer. The structure further includes a second silicide layer disposed within a bottom portion of the epitaxial region and a second conductive structure disposed on a bottom surface of the second silicide layer and traversing through the substrate, where the second conductive structure includes a first metal layer in contact with the second silicide layer and a second metal layer in contact with the first metal layer.
    Type: Grant
    Filed: June 17, 2022
    Date of Patent: April 8, 2025
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Kan-Ju Lin, Lin-Yu Huang, Min-Hsuan Lu, Wei-Yip Loh, Hong-Mao Lee, Harry Chien
  • Publication number: 20250107721
    Abstract: A pulse pressure measuring apparatus including a plurality of pressing elements, a plurality of pressure sensors, and a processing unit is provided. The pressing elements are used to press the site to be measured, and each pressing element has a position coordinate Pi (i=1, 2, 3 . . . ). The pressure sensors are configured to respectively measure pressure on the pressing elements to generate measured values of pressure intensity Ii (i=1, 2, 3 . . . ) at the position coordinates Pi (i=1, 2, 3 . . . ). The processing unit utilizes the position coordinates Pi (i=1, 2, 3 . . . ) and the measured values of pressure intensity Ii (i=1, 2, 3 . . . ) to determine the blood vessel locus.
    Type: Application
    Filed: March 28, 2024
    Publication date: April 3, 2025
    Applicant: GUANGZHOU LUXVISIONS INNOVATION TECHNOLOGY LIMITED
    Inventors: Chih-Ju Lin, Shih-Chieh Yen, Yi-Wei Liu, Wei-Han Wu
  • Publication number: 20250105019
    Abstract: A method is provided. The method includes: receiving a semiconductor structure having a first material and a second material; performing a first etch on the first material for a first duration under a first etching chemistry; and performing a second etch on the second material for a second duration under a second etching chemistry, wherein the first material includes a first incubation time and the second material includes a second incubation time greater than the first incubation time under the first etching chemistry. The first material includes a third incubation time and the second material includes a fourth incubation time less than the third incubation time under the second etching chemistry.
    Type: Application
    Filed: December 10, 2024
    Publication date: March 27, 2025
    Inventors: HAN-YU LIN, LI-TE LIN, TZE-CHUNG LIN, FANG-WEI LEE, YI-LUN CHEN, JUNG-HAO CHANG, YI-CHEN LO, FO-JU LIN, KENICHI SANO, PINYEN LIN
  • Publication number: 20250096808
    Abstract: A voltage-controlled oscillator includes an input circuit, a first current supply circuit, a second current supply circuit, a filtering circuit, and an oscillating circuit. The input circuit includes an operational amplifier and a first input transistor. The operational amplifier generates an output voltage according to an input voltage and a feedback voltage. The first input transistor generates an input current according to the output voltage and a power supply voltage. The first current supply circuit generates a first output current according to the input current. The second current supply circuit generates a second output current according to the input current. The filtering circuit couples to the input circuit and the second current supply circuit, and decrease an influence caused by a variation of the input current on the second current supply circuit. The oscillating circuit generates an output clock according to the first output current and the second output current.
    Type: Application
    Filed: September 3, 2024
    Publication date: March 20, 2025
    Inventors: KUO-WEI WU, Yen-Ju Lin
  • Publication number: 20250090022
    Abstract: An eye detection physiological information capture device includes a first light plate assembly, and a second light plate assembly arranged in a housing. The first light plate assembly includes a first light source module, and a signal detection module. The signal detection module detects the reflection of light emitted from the first light source module towards an eye. The second light plate assembly includes a second light source module, a lens assembly, a first camera module, and a second camera module. The lens assembly is arranged to enable light rays from the second light source module to respectively irradiate the eye. The first camera module can capture a three-dimensional image of the eye and the second camera module can capture a fundus image of the eye by detecting the reflection of light emitted from the second light source module towards the eye.
    Type: Application
    Filed: April 16, 2024
    Publication date: March 20, 2025
    Applicant: PolyVisions Technology Co., Ltd.
    Inventors: Chih-Ju Lin, Shih-Chieh Yen, Chen-Fu Huang
  • Patent number: 12255070
    Abstract: In a semiconductor structure, a first conductive feature is formed in a trench by PVD and a glue layer is then deposited on the first conductive feature in the trench before CVD deposition of a second conductive feature there-over. The first conductive feature acts as a protection layer to keep silicide from being damaged by later deposition of metal or a precursor by CVD. The glue layer extends along the extent of the sidewall to enhance the adhesion of the second conductive features to the surrounding dielectric layer.
    Type: Grant
    Filed: September 30, 2021
    Date of Patent: March 18, 2025
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Min-Hsuan Lu, Kan-Ju Lin, Lin-Yu Huang, Sheng-Tsung Wang, Hung-Yi Huang, Chih-Wei Chang, Ming-Hsing Tsai, Chih-Hao Wang
  • Patent number: 12250776
    Abstract: A substrate structure and a cutting method thereof are provided. The cutting method includes the following steps. A first substrate structure is provided, wherein the first substrate structure includes a glass substrate and a redistribution layer disposed on the glass substrate. A laser process is performed on the glass substrate to form a modified region on the glass substrate. A wet etching process is performed on the modified region of the glass substrate to remove the modified region and form a plurality of second substrate structures.
    Type: Grant
    Filed: May 15, 2023
    Date of Patent: March 11, 2025
    Assignee: UNIMICRON TECHNOLOGY CORP.
    Inventors: Jeng-Ting Li, Chi-Hai Kuo, Cheng-Ta Ko, Pu-Ju Lin
  • Patent number: 12243838
    Abstract: A circuit substrate structure includes a circuit substrate, at least two chips, and a bridge element. The circuit substrate has a first surface and a second surface opposite to each other. The chips are arranged in parallel on the first surface of the circuit substrate and electrically connected to the circuit substrate. The chips have active surfaces, back surfaces opposite to the active surfaces, and side surfaces connecting the active surfaces and the back surfaces. The chips include side circuits. The side circuits are arranged on the side surfaces and have first ends and second ends, the first ends extend to the active surfaces along the side surfaces, and the second ends extend to the back surfaces along the side surfaces. The bridge element is arranged on the back surfaces of the chips and electrically connected to the active surfaces of the chips through the side circuits.
    Type: Grant
    Filed: January 4, 2022
    Date of Patent: March 4, 2025
    Assignee: Unimicron Technology Corp.
    Inventors: Tzyy-Jang Tseng, Pu-Ju Lin, Cheng-Ta Ko, John Hon-Shing Lau
  • Publication number: 20250048539
    Abstract: A printed circuit board comprising a differential microstrip pair including a neck-down area and an ultraviolet glue coating a portion of the neck-down area of the differential microstrip pair to control an impedance of the differential microstrip pair.
    Type: Application
    Filed: July 31, 2023
    Publication date: February 6, 2025
    Inventors: Pei-Ju Lin, Chang-Hsien Chen, Bhyrav Mutnury, Yi-Tang Chen
  • Publication number: 20250046301
    Abstract: A display device includes a diffusion layer providing a single well, an optical element configured to receive light and output the received image light including a concentric series of lens segments made up of active facets, and a waveguide having an in-coupling grating and a waveguide body optically coupled to the image light, where a polarizing component is disposed over an output surface of the optical element. A method to improve a yield of silicon backplane displays includes connecting a diode having a resolution to a backplane and repairing a defect on a pixel display area by dividing the pixel display area into at least one subcircuit, while improving geometry stylization transfer for 3D models of real-world environments. A method for suppressing crosstalk for user conversations includes receiving multiple speech signals captured by multiple microphones and generating directional data for the multiple speech signals based on spatial filtering.
    Type: Application
    Filed: July 29, 2024
    Publication date: February 6, 2025
    Inventors: Balasubramanian Sivakumar, Min Hyuk Choi, Gang Chen, Gyungmin Kim, Ahmet Tura, Hai Jung In, Weiwei Wang, Suhui Lee, Woong Hwang, Wanyue Song, Wai Sze Tiffany Lam, Wanli Chi, Nikolaos Sarafianos, Rakesh Ranjan, Alexander Sorkine Hornung, Seonghyeon Nam, Hyunyoung Jung, Ruiming Xie, Ju Lin, Niko Moritz, Frank Torsten Bernd Seide
  • Patent number: 12218017
    Abstract: The invention discloses a glass carrier having a protection structure, comprising a glass body and a protection layer. The glass body has a top surface, a bottom surface, and a lateral surface. The protection layer covers the lateral surface of the glass body. The protection layer is a hard material with a stiffness coefficient higher than a stiffness coefficient of the glass body. The invention further discloses a manufacturing method of a glass carrier having a protection structure, comprising the following steps: covering the protection layer around the lateral surface of the glass body, wherein the protection layer is the hard material with the stiffness coefficient higher than the stiffness coefficient of the glass body.
    Type: Grant
    Filed: January 27, 2022
    Date of Patent: February 4, 2025
    Assignee: UNIMICRON TECHNOLOGY CORP.
    Inventors: Wen Yu Lin, Kai-Ming Yang, Pu-Ju Lin
  • Patent number: 12218219
    Abstract: The present disclosure describes a semiconductor structure and a method for forming the same. The method can include forming a fin structure over a substrate. The fin structure can include first and second sacrificial layers. The method can further include forming a recess structure in a first portion of the fin structure, selectively etching the first sacrificial layer of a second portion of the fin structure over the second sacrificial layer of the second portion of the fin structure, and forming an inner spacer layer over the etched first sacrificial layer with the second sacrificial layer of the second portion of the fin structure being exposed.
    Type: Grant
    Filed: August 27, 2021
    Date of Patent: February 4, 2025
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Jung-Hao Chang, Fo-Ju Lin, Fang-Wei Lee, Li-Te Lin, Pinyen Lin
  • Publication number: 20250040238
    Abstract: In an embodiment, a device includes: lower semiconductor nanostructures including a first semiconductor material; a lower epitaxial source/drain region adjacent the lower semiconductor nanostructures, the lower epitaxial source/drain region having a first conductivity type; upper semiconductor nanostructures including a second semiconductor material, the second semiconductor material different from the first semiconductor material; and an upper epitaxial source/drain region adjacent the upper semiconductor nanostructures, the upper epitaxial source/drain region having a second conductivity type, the second conductivity type being opposite the first conductivity type.
    Type: Application
    Filed: July 28, 2023
    Publication date: January 30, 2025
    Inventors: Yu-Wei Lu, Kenichi Sano, Tze-Chung Lin, Fang-Wei Lee, Chia-Chien Kuang, Yi-Chen Lo, Fo-Ju Lin, Li-Te Lin, Pinyen Lin
  • Patent number: D1062757
    Type: Grant
    Filed: August 12, 2022
    Date of Patent: February 18, 2025
    Assignee: HTC Corporation
    Inventors: Ying-Jing Wang, Fang-Ju Lin, Yun-Jung Lee, Yu-Chien Huang, Kuan-Yi Lien