Patents by Inventor An Kuo
An Kuo has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20250190605Abstract: A computer-implemented method and system for storing verifiable data. The method comprises: generating a metadata object; generating at least one claim object; generating a proof object; generating multiple identifiers, wherein each of the identifiers corresponds to the metadata object, the at least one claim object and the proof object, respectively; and generating a Merkle DAG based on the multiple identifiers, the metadata object, the at least one claim object, and the proof object, wherein the Merkle DAG is constructed by nodes which are created based on the multiple identifiers.Type: ApplicationFiled: March 8, 2024Publication date: June 12, 2025Inventors: Chu George Kai, Feng-Chia Chang, An-Kuo Li
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Patent number: 12324092Abstract: An integrated circuit is disclosed. The integrated circuit is coupled to a circuit board. The circuit board includes several signal pair channels. The integrated circuit includes several output terminals and a control circuit. The control circuit is configured to configure several output signals output to several signal pair channels by several output terminals, so that a first signal pair channel and a second signal pair channel of several signal pair channels receive and output several output signals, so that a third signal pair channel of several signal pair channels shields an interference between the first signal pair channel and the second signal pair channel. The third signal pair channel is adjacent to the first signal pair channel and the second signal pair channel, and the third signal pair channel is located between the first signal pair channel and the second signal pair channel.Type: GrantFiled: April 17, 2023Date of Patent: June 3, 2025Assignee: Realtek Semiconductor CorporationInventors: Li Chung Chang, Shih Min Yen, Meng An Kuo
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Publication number: 20250167146Abstract: A first wafer having a two-dimensional array of first semiconductor dies including arrays of first top metal bonding pads attached to a top surface of a first carrier wafer. A second wafer having a two-dimensional array of second semiconductor dies including arrays of second top metal bonding pads and arrays of second bottom metal bonding pads bonded to the first wafer by performing a first metal-to-metal bonding process in which the arrays of first top metal bonding pads are bonded to the arrays of second bottom metal bonding pads through first intermetallic diffusion. A third wafer having a two-dimensional array of third semiconductor dies including arrays of third bottom metal bonding pads bonded to the second wafer by performing a second metal-to-metal bonding process in which the arrays of second top metal bonding pads are bonded to the arrays of third bottom metal bonding pads through second intermetallic diffusion.Type: ApplicationFiled: November 21, 2023Publication date: May 22, 2025Inventors: Sheng-An Kuo, Chen-Sheng Lin, Chao-Wen Shih, Kuo-Chiang Ting, Yen-Ming Chen
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Publication number: 20250167150Abstract: A first wafer having a first portion closer to a first surface and a thicker second portion connected with the first portion and closer to the second surface opposite to the first surface is provided. A second wafer is provided to bond with the first wafer. An edge trimming process is performed to form a trench penetrating through the second wafer and extending beyond the first portion and extending into the second portion. After bonding dies to the second wafer, a filling material is formed over the dies and the first and second wafers, wrapping around and between the dies, covering the first and second wafers, and partially filling the trench. A wafer thinning process is performed to remove the second portion and partially remove the filling material in the trench to level the surface of the thinned first wafer with the surface of the thinned filling material.Type: ApplicationFiled: November 21, 2023Publication date: May 22, 2025Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Sheng-An Kuo, Eva Wang, Shi-Dong Hong, Chen-Sheng Lin, Chao-Wen Shih, Kuo-Chiang Ting
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Publication number: 20250163498Abstract: Disclosed are compositions and methods for detecting nucleic acid, or detecting the presence or absence of a nuclease. Specifically, disclosed herein are nucleic acid-metal nanocluster probes. which comprise a nucleic acid probe with metal nanoclusters associated therewith. These nucleic acid-metal nanocluster probes can be used to detect a variety of cleavage events. and can also be used to detect hybridization to the probe.Type: ApplicationFiled: January 4, 2023Publication date: May 22, 2025Inventors: Hsin-Chih Yeh, Soonwoo HONG, Yuan-I CHEN, Yu-An KUO, Trung Duc NGUYEN
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Publication number: 20250140743Abstract: A structure including a first semiconductor die, second semiconductor dies, a bridge die, and a gap filling material is provided. The first semiconductor die includes integrated circuit regions. The second semiconductor dies are disposed over and electrically connected to the first semiconductor die. The bridge die is disposed over and electrically connected to the first semiconductor die, and the integrated circuit regions are electrically connected to each other through the bridge die. The gap filling material is disposed on the first semiconductor die to laterally encapsulate the bridge die and the second semiconductor dies.Type: ApplicationFiled: November 1, 2023Publication date: May 1, 2025Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Sheng-An Kuo, Chao-Wen Shih, Kuo-Chiang Ting, Yen-Ming Chen
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Publication number: 20250069975Abstract: A semiconductor structure including a first semiconductor die, a second semiconductor die, a passivation layer, an anti-arcing pattern, and conductive terminals is provided. The second semiconductor die is stacked over the first semiconductor die. The passivation layer covers the second semiconductor die and includes first openings for revealing pads of the second semiconductor die. The anti-arcing pattern is disposed over the passivation layer. The conductive terminals are disposed over and electrically connected to the pads of the second semiconductor die.Type: ApplicationFiled: November 12, 2024Publication date: February 27, 2025Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Sheng-An Kuo, Ching-Jung Yang, Hsien-Wei Chen, Jie Chen, Ming-Fa Chen
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Patent number: 12176257Abstract: A semiconductor structure including a first semiconductor die, a second semiconductor die, a passivation layer, an anti-arcing pattern, and conductive terminals is provided. The second semiconductor die is stacked over the first semiconductor die. The passivation layer covers the second semiconductor die and includes first openings for revealing pads of the second semiconductor die. The anti-arcing pattern is disposed over the passivation layer. The conductive terminals are disposed over and electrically connected to the pads of the second semiconductor die.Type: GrantFiled: July 14, 2023Date of Patent: December 24, 2024Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Sheng-An Kuo, Ching-Jung Yang, Hsien-Wei Chen, Jie Chen, Ming-Fa Chen
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Publication number: 20240378805Abstract: A 3D road scene generation system (1) for simulating a real environment is presented. The 3D road scene generation system (1) generates 3D topographic data (41) based on a topographic map (40) , generates 3D route data including a target route (43) based on road network data (42) , generates 3D landscape data (44) based on landscape data, and executes an integrating process on these data to generate the 3D road scene data (46, 49) for presenting terrain changes and scenery along the target route (43) .Type: ApplicationFiled: May 12, 2023Publication date: November 14, 2024Inventors: Chun-Cheng CHEN, Ting-Hung LEE, Shao-Hong YANG, Tzu-An KUO
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Publication number: 20240172357Abstract: An integrated circuit is disclosed. The integrated circuit is coupled to a circuit board. The circuit board includes several signal pair channels. The integrated circuit includes several output terminals and a control circuit. The control circuit is configured to configure several output signals output to several signal pair channels by several output terminals, so that a first signal pair channel and a second signal pair channel of several signal pair channels receive and output several output signals, so that a third signal pair channel of several signal pair channels shields an interference between the first signal pair channel and the second signal pair channel. The third signal pair channel is adjacent to the first signal pair channel and the second signal pair channel, and the third signal pair channel is located between the first signal pair channel and the second signal pair channel.Type: ApplicationFiled: April 17, 2023Publication date: May 23, 2024Inventors: Li Chung CHANG, Shih Min YEN, Meng An KUO
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Publication number: 20240035971Abstract: A fluorescence lifetime imaging microscopy system comprises a microscope comprising an excitation source configured to direct an excitation energy to an imaging target, and a detector configured to measure emissions of energy from the imaging target, and a non-transitory computer-readable medium with instructions stored thereon, which perform steps comprising collecting a quantity of measured emissions of energy from the imaging target as measured data, providing a trained neural network configured to calculate fluorescent decay parameters from the quantity of measured emissions of energy, providing the data to the trained neural network, and calculating at least one fluorescence lifetime parameter with the neural network from the measured data, wherein the measured data comprises an input fluorescence decay histogram, and wherein the neural network was trained by a generative adversarial network. A method of training a neural network and a method of acquiring an image are also described.Type: ApplicationFiled: September 17, 2021Publication date: February 1, 2024Inventors: Hsin-Chih Yeh, Yuan-I Chen, Yin-Jui Chang, Shih-Chu Liao, Trung Duc Nguyen, Soonwoo Hong, Yu-An Kuo, Hsin-Chin Li
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Patent number: 11817496Abstract: A high voltage semiconductor device includes a semiconductor substrate, a gate structure, a drift region, a drain region, and an isolation structure. The gate structure is disposed on the semiconductor substrate. The drift region is disposed in the semiconductor substrate and partially disposed at a side of the gate structure. The drain region is disposed in the drift region. The isolation structure is at least partially disposed in the drift region. A part of the isolation structure is disposed between the drain region and the gate structure. The isolation structure includes a curved bottom surface.Type: GrantFiled: November 1, 2021Date of Patent: November 14, 2023Assignee: UNITED MICROELECTRONICS CORP.Inventors: Ya-Hsin Huang, Chen-An Kuo, Po-Chun Lai
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Publication number: 20230360986Abstract: A semiconductor structure including a first semiconductor die, a second semiconductor die, a passivation layer, an anti-arcing pattern, and conductive terminals is provided. The second semiconductor die is stacked over the first semiconductor die. The passivation layer covers the second semiconductor die and includes first openings for revealing pads of the second semiconductor die. The anti-arcing pattern is disposed over the passivation layer. The conductive terminals are disposed over and electrically connected to the pads of the second semiconductor die.Type: ApplicationFiled: July 14, 2023Publication date: November 9, 2023Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Sheng-An Kuo, Ching-Jung Yang, Hsien-Wei Chen, Jie Chen, Ming-Fa Chen
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Patent number: 11804526Abstract: A semiconductor device includes a semiconductor substrate, a gate structure, a source region, a drain region, and a plurality of field plates. The gate structure is disposed on the semiconductor substrate. The source region and the drain region are disposed in the semiconductor substrate and located at two opposite sides of the gate structure in a first direction respectively. The field plates are disposed on the semiconductor substrate. Each of the field plates is partly located above the gate structure and partly located between the gate structure and the drain region. The gate structure is electrically connected with at least one of the field plates, and the source region is electrically connected with at least one of the field plates.Type: GrantFiled: August 25, 2022Date of Patent: October 31, 2023Assignee: UNITED MICROELECTRONICS CORP.Inventors: Yi-Chieh Wang, Po-Chun Lai, Ke-Feng Lin, Chen-An Kuo, Ze-Wei Jhou
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Patent number: 11798998Abstract: A semiconductor device includes a semiconductor substrate, a gate structure, a source region, a drain region, and a plurality of field plates. The gate structure is disposed on the semiconductor substrate. The source region and the drain region are disposed in the semiconductor substrate and located at two opposite sides of the gate structure in a first direction respectively. The field plates are disposed on the semiconductor substrate. Each of the field plates is partly located above the gate structure and partly located between the gate structure and the drain region. The gate structure is electrically connected with at least one of the field plates, and the source region is electrically connected with at least one of the field plates.Type: GrantFiled: August 24, 2022Date of Patent: October 24, 2023Assignee: UNITED MICROELECTRONICS CORP.Inventors: Yi-Chieh Wang, Po-Chun Lai, Ke-Feng Lin, Chen-An Kuo, Ze-Wei Jhou
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Patent number: 11791386Abstract: A semiconductor device includes a semiconductor substrate, a gate structure, a source region, a drain region, and a plurality of field plates. The gate structure is disposed on the semiconductor substrate. The source region and the drain region are disposed in the semiconductor substrate and located at two opposite sides of the gate structure in a first direction respectively. The field plates are disposed on the semiconductor substrate. Each of the field plates is partly located above the gate structure and partly located between the gate structure and the drain region. The gate structure is electrically connected with at least one of the field plates, and the source region is electrically connected with at least one of the field plates.Type: GrantFiled: August 24, 2022Date of Patent: October 17, 2023Assignee: UNITED MICROELECTRONICS CORP.Inventors: Yi-Chieh Wang, Po-Chun Lai, Ke-Feng Lin, Chen-An Kuo, Ze-Wei Jhou
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Patent number: 11769704Abstract: A semiconductor structure including a first semiconductor die, a second semiconductor die, a passivation layer, an anti-arcing pattern, and conductive terminals is provided. The second semiconductor die is stacked over the first semiconductor die. The passivation layer covers the second semiconductor die and includes first openings for revealing pads of the second semiconductor die. The anti-arcing pattern is disposed over the passivation layer. The conductive terminals are disposed over and electrically connected to the pads of the second semiconductor die.Type: GrantFiled: February 9, 2022Date of Patent: September 26, 2023Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Sheng-An Kuo, Ching-Jung Yang, Hsien-Wei Chen, Jie Chen, Ming-Fa Chen
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Publication number: 20230267893Abstract: A driving method of a display device comprises the following steps. A period to turn off a backlight module is set. An overdrive voltage is applied, and an overdrive time required for a liquid crystal to change from a first target gray scale to a second target gray scale is obtained. A turn-off time point for turning off the backlight module is adjusted so that at least a part of the period when the backlight module is turned off overlaps the overdrive time.Type: ApplicationFiled: April 1, 2022Publication date: August 24, 2023Applicant: Qisda CorporationInventor: Min-An KUO
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Patent number: 11670713Abstract: An LDMOS includes a semiconductor substrate. A well is disposed within the semiconductor substrate. A body region is disposed within the well. A first gate electrode is disposed on the semiconductor substrate. A source electrode is disposed at one side of the first gate electrode. The source electrode includes a source contact area and numerous vias. The vias connect to the source contact area. The vias extend into the semiconductor substrate. A first drain electrode is disposed at another side of the first gate electrode and is opposed to the source electrode.Type: GrantFiled: August 10, 2022Date of Patent: June 6, 2023Assignee: UNITED MICROELECTRONICS CORP.Inventors: Chung-Yen Feng, Chen-An Kuo, Ching-Wei Teng, Po-Chun Lai
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Patent number: D1023099Type: GrantFiled: June 3, 2020Date of Patent: April 16, 2024Assignee: VIA TECHNOLOGIES, INC.Inventors: Chia-Yi Lin, Neng-An Kuo