Abstract: A light-emitting device includes an epitaxial structure having a first surface and a second surface that is opposite to the first surface. The epitaxial structure includes, along a first direction from the first surface to the surface, a first-type semiconductor layer, an active layer, and a second-type semiconductor layer including a capping layer. The capping layer includes at least Ni number of sub-layers arranged in the first direction, where N1?2. Each of the sub-layers of the capping layer contains a material represented by Aly1Ga1-y1InP, where 0<y1?1. The capping layer has an Al content which increases and then remains constant along the first direction. A light-emitting apparatus includes the light-emitting device is also provided.

Abstract: A device includes a first III-V compound layer, a second III-V compound layer, a dielectric layer, a contact, a metal-containing layer, and a metal contact. The second III-V compound layer is over the first III-V compound layer. The dielectric layer is over the second III-V compound layer. The contact extends through the dielectric layer to the second III-V compound layer. The contact is in contact with a top surface of the dielectric layer and an inner sidewall of the dielectric layer. The metal-containing layer is over and in contact with the contact, and a portion of the metal-containing layer is directly above the dielectric layer. The metal contact is over and in contact with the metal-containing layer.

Abstract: A semiconductor structure may include an interposer including on-interposer bump structures, at least one semiconductor die bonded to a first subset of the on-interposer bump structures through first solder material portions, at least one spacer die bonded to a second subset of the on-interposer bump structures through second solder material portions, and a molding compound die frame laterally surrounding each of the at least one semiconductor die and the at least one spacer die. Each of the at least one semiconductor die includes a respective set of transistors and a respective set of metal interconnect structures. Each of the at least one spacer die is free from any transistor therein.

Abstract: A semiconductor device package is provided, including a package substrate, a semiconductor device, a metal lid, and a metal thermal interface material (TIM). The package substrate has a first surface. The semiconductor device is disposed over the first surface of the package substrate. The metal lid is disposed over the semiconductor device and the package substrate. The metal TIM is interposed between the metal lid and the top surface of the semiconductor device for bonding the metal lid and the semiconductor device. A shape of the lateral sidewall of the metal TIM in a longitudinal section is concave arc, and the outermost point of the lateral sidewall is within the boundary of the semiconductor device.

Abstract: Package structures and methods of forming package structures are discussed. A package structure, in accordance with some embodiments, includes a large package component, such as a CoWoS, adhered to a large package substrate, such as a printed circuit board, an underfill material disposed between the large package component and the large package substrate, and a stress-release structure with high elongation values formed from photolithography encapsulated by the underfill material. The stress-release structure helping to reduce stress in the underfill material to reduce the risk of underfill cracking caused by the difference in coefficients of thermal expansion between the large package component and the large package substrate.

Abstract: Package structures and methods of forming package structures are discussed. A package structure, in accordance with some embodiments, includes a package component with one or more integrated circuits adhered to a package substrate, a hybrid thermal interface material utilizing a combination of polymer based material with high elongation values and metal based material with high thermal conductivity values. The polymer based thermal interface material placed on the edge of the package component contains the metal based thermal interface material in liquid form.

Abstract: An operating method of an under-display camera system includes: providing a raw data by a pixel array; generating, by a plurality of color filters respectively disposed on a plurality of first photodiodes of the pixel array, a color information in accordance with the raw data; generating, by a plurality of first narrowband filters respectively disposed on a plurality of second photodiodes of the pixel array, a first narrowband information in accordance with the raw data, wherein a spectrum linewidth of the plurality of first narrowband filters is in a range from 5 nm to 70 nm; reconstructing an edge information from the first narrowband information based on one of a plurality of diffraction patterns provided by a database unit of a point spread function; and obtaining an image by combining the edge information with the color information.

Abstract: In an embodiment, a method of forming an integrated circuit package includes: attaching a first carrier to a package component, the package component comprising: an interposer; a first semiconductor die attached to a first side of the interposer; a second semiconductor die attached to the first side of the interposer; an encapsulant encapsulating the first semiconductor die and the second semiconductor die; and conductive connectors attached to a second side of the interposer; attaching a second carrier to a package substrate, the package substrate comprising bond pads; bonding the conductive connectors of the package component to the bond pads of the package substrate by reflowing the conductive connectors while the first carrier is attached to the package component and while the second carrier is attached to the package substrate; removing the first carrier; and removing the second carrier.

Abstract: In an embodiment, a device includes: an integrated circuit die including a die connector; a first through via adjacent the integrated circuit die; an encapsulant encapsulating the first through via and the integrated circuit die; and a redistribution structure on the encapsulant, the redistribution structure including a redistribution line, the redistribution line physically and electrically coupled to the die connector of the integrated circuit die, the redistribution line electrically isolated from the first through via, the redistribution line crossing over the first through via.

Abstract: A capacitor structure and method of forming the capacitor structure is provided, including a providing a doped region of a substrate having a two-dimensional trench array with a plurality of segments defined therein. Each of the plurality of segments has an array of a plurality of recesses extending along the substrate, where the plurality of segments are rotationally symmetric about a center of the two-dimensional trench array. A first conducting layer is presented over the surface and a bottom and sidewalls of the recesses and is insulated from the substrate by a first dielectric layer. A second conducting layer is presented over the first conducting layer and is insulated by a second dielectric layer. First and second contacts respectively connect to an exposed top surface of the first conducting layer and second conducting layer. A third contact connects to the substrate within a local region to the capacitor structure.

Abstract: An operating method of an under-display camera system includes: providing a raw data by a pixel array; generating, by a plurality of color filters respectively disposed on a plurality of first photodiodes of the pixel array, a color information in accordance with the raw data; generating, by a plurality of first narrowband filters respectively disposed on a plurality of second photodiodes of the pixel array, a first narrowband information in accordance with the raw data, wherein a spectrum linewidth of the plurality of first narrowband filters is in a range from 5 nm to 70 nm; reconstructing an edge information from the first narrowband information based on one of a plurality of diffraction patterns provided by a database unit of a point spread function; and obtaining an image by combining the edge information with the color information.

Abstract: Embodiments provide metal features which dissipate heat generated from a laser drilling process for exposing dummy pads through a dielectric layer. Because the dummy pads are coupled to the metal features, the metal features act as a heat dissipation feature to pull heat from the dummy pad. As a result, reduction in heat is achieved at the dummy pad during the laser drilling process.

Abstract: A method for forming a semiconductor device package is provided. The method includes bonding a semiconductor device to a package substrate; placing a metal lid over the semiconductor device and the package substrate with a metal thermal interface material (TIM) provided between the metal lid and the semiconductor device; heating the metal TIM to melt the metal TIM; pressing the metal lid downward so that the molten metal TIM flows toward the boundary of the semiconductor device, and the outermost point of the lateral sidewall of the molten metal TIM extends beyond the boundary of the semiconductor device; lifting the metal lid upward so that the molten metal TIM flows back, and the outermost point of the lateral sidewall is within the boundary of the semiconductor device; and bonding the metal lid to the semiconductor device through the metal TIM by curing the molten metal TIM.

Abstract: An image sensor includes a storage device, where the storage device includes a memory element, a first dielectric layer and a light shielding element. The memory element includes a storage node and a storage transistor gate, where the storage transistor gate is located over the storage node. The first dielectric layer is located over a portion of the storage transistor gate. The light shielding element is located on the first dielectric layer and includes a semiconductor layer. The semiconductor layer is electrically isolated from the memory element, where the light shielding element is overlapped with at least a part of a perimeter of the storage transistor gate in a vertical projection on a plane along a stacking direction of the memory element and the light shielding element, and the stacking direction is normal to the plane.

Abstract: Structures and methods for reducing thermal expansion mismatch during chip scale packaging are disclosed. In one example, a semiconductor structure is disclosed. The semiconductor structure includes a first metal layer over a substrate, a dielectric region, and a polymer region. The first metal layer comprises a first device metal structure. The dielectric region is formed over the first metal layer. The polymer region is formed over the dielectric region. The dielectric region comprises a plurality of metal layers and an inter-metal dielectric layer comprising dielectric material between each pair of two adjacent metal layers in the plurality of metal layers. Each of the plurality of metal layers comprises a dummy metal structure over the first device metal structure. The dummy metal structures in each pair of two adjacent metal layers in the plurality of metal layers shield respectively two non-overlapping portions of the first device metal structure from a top view of the semiconductor structure.

Abstract: A capacitor structure and method of forming the capacitor structure is provided, including a providing a doped region of a substrate having a two-dimensional trench array with a plurality of segments defined therein. Each of the plurality of segments has an array of a plurality of recesses extending along the substrate, where the plurality of segments are rotationally symmetric about a center of the two-dimensional trench array. A first conducting layer is presented over the surface and a bottom and sidewalls of the recesses and is insulated from the substrate by a first dielectric layer. A second conducting layer is presented over the first conducting layer and is insulated by a second dielectric layer. First and second contacts respectively connect to an exposed top surface of the first conducting layer and second conducting layer. A third contact connects to the substrate within a local region to the capacitor structure.

Abstract: The optical device includes a first photodiode, a second photodiode, and a hybrid absorber. The hybrid absorber is disposed above the first photodiode and the second photodiode. The hybrid absorber includes a color filter layer and a plurality of metal-insulator-metal structures. The color filter layer includes a first color filter disposed on the first photodiode and a second color filter disposed on the second photodiode, in which the first color filter is different from the second color filter. The plurality of metal-insulator-metal structures are disposed above the first photodiode and free of disposed above the second photodiode.

Abstract: An image sensor includes a storage device, where the storage device includes a memory element, a first dielectric layer and a light shielding element. The memory element includes a storage node and a storage transistor gate, where the storage transistor gate is located over the storage node. The first dielectric layer is located over a portion of the storage transistor gate. The light shielding element is located on the first dielectric layer and includes a semiconductor layer. The semiconductor layer is electrically isolated from the memory element, where the light shielding element is overlapped with at least a part of a perimeter of the storage transistor gate in a vertical projection on a plane along a stacking direction of the memory element and the light shielding element, and the stacking direction is normal to the plane.

Abstract: Structures and methods for reducing thermal expansion mismatch during chip scale packaging are disclosed. In one example, a semiconductor structure is disclosed. The semiconductor structure includes a first metal layer over a substrate, a dielectric region, and a polymer region. The first metal layer comprises a first device metal structure. The dielectric region is formed over the first metal layer. The polymer region is formed over the dielectric region. The dielectric region comprises a plurality of metal layers and an inter-metal dielectric layer comprising dielectric material between each pair of two adjacent metal layers in the plurality of metal layers. Each of the plurality of metal layers comprises a dummy metal structure over the first device metal structure. The dummy metal structures in each pair of two adjacent metal layers in the plurality of metal layers shield respectively two non-overlapping portions of the first device metal structure from a top view of the semiconductor structure.

Abstract: A meta optical device is provided. The meta optical device includes an array of meta structures. Each of the meta structures includes a plurality of stacked layers at least including a first layer with a first refractive index and a second layer with a second refractive index. The first refractive index and the second refractive index are different.