Abstract: An integrated fan-out package includes a first redistribution structure, a die, conductive structures, an encapsulant, and a second redistribution structure. The first redistribution structure has first regions and a second region surrounding the first regions. A metal density in the first regions is smaller than a metal density in the second region. The die is disposed over the first redistribution structure. The conductive structures are disposed on the first redistribution structure to surround the die. Vertical projections of the conductive structures onto the first redistribution structure fall within the first regions of the first redistribution structure. The encapsulant encapsulates the die and the conductive structures. The second redistribution structure is disposed on the encapsulant, the die, and the conductive structures.

Abstract: A package includes a frontside redistribution layer (RDL) structure, a semiconductor die on the frontside RDL structure, and a backside RDL structure on the semiconductor die including a first RDL, and a backside connector extending from a distal side of the first RDL and including a tapered portion having a width that decreases in a direction away from the first RDL, wherein the tapered portion includes a contact surface at an end of the tapered portion. A method of forming the package may include forming the backside redistribution layer (RDL) structure, attaching a semiconductor die to the backside RDL structure, forming an encapsulation layer around the semiconductor die on the backside RDL structure, and forming a frontside RDL structure on the semiconductor die and the encapsulation layer.

Abstract: A semiconductor package includes a redistribution structure and an encapsulated die electrically connected to the redistribution structure. The redistribution structure includes a first conductive pad, first and second conductive vias, and a first dielectric layer. The first conductive pad includes opposing first and second sides, the first conductive via lands on the first side of the first conductive pad and is tapered in a direction from the first side toward the second side. The second conductive via lands on the second side of the first conductive pad and is tapered in a direction from the second side toward the first side. The first dielectric layer laterally covers the first conductive pad and the first conductive via, and the first dielectric layer includes opposing first and second surfaces. The encapsulated die is disposed below the first side of the first conductive via.

Abstract: A micro-bolometer and a thermal sensing method thereof are provided. Each of switching circuits switches connection relationship between a first connection point or a second connection point of a corresponding thermal sensing pixel and different signal transmission lines and a shared connection line, so as to adjust the connection mode of the thermal sensing pixels, the first signal transmission line, the second signal transmission line and the at least one shared connection line, and thus to change a sensing signal provided by the thermal sensing pixels.

Abstract: A package structure including a semiconductor die, a redistribution layer structure and an electronic device is provided. The semiconductor die is laterally encapsulated by an insulating encapsulation. The redistribution layer structure is disposed on the semiconductor die and the insulating encapsulation. The redistribution layer structure includes a backside dielectric layer, inter-dielectric layers and redistribution conductive layers embedded in the backside dielectric layer and the inter-dielectric layers. The electronic device is disposed over the backside dielectric layer and electrically connected to an outermost redistribution conductive layer among the redistribution conductive layers, wherein the outermost redistribution conductive layer is embedded in the backside dielectric layer, and the backside dielectric layer comprises a ring-shaped recess covered by the outermost redistribution conductive layer.

Abstract: A wafer defect detection device adapted for detecting a sample to be tested including two detection features is provided. The wafer defect detection device includes a stage adapted for holding the sample to be tested, a light source module configured to output a detection light to the sample to be tested and reflect a reflected light, and an image sensor disposed on a path of the reflected light and adapted for receiving an image frame. The detection light includes spectra of a first light and a second light, which have two different peak wavelengths. The spectrum of the first light is adapted for detecting one of the detection features. The spectrum of the second light is adapted for detecting other one of the detection features. Luminous intensities of the first light and the second light are independently controlled. The reflected light includes the image frame, which displays the detection features.

Abstract: In an embodiment, a device includes: an integrated circuit die; an encapsulant at least partially surrounding the integrated circuit die, the encapsulant including fillers having an average diameter; a through via extending through the encapsulant, the through via having a lower portion of a constant width and an upper portion of a continuously decreasing width, a thickness of the upper portion being greater than the average diameter of the fillers; and a redistribution structure including: a dielectric layer on the through via, the encapsulant, and the integrated circuit die; and a metallization pattern having a via portion extending through the dielectric layer and a line portion extending along the dielectric layer, the metallization pattern being electrically coupled to the through via and the integrated circuit die.

Abstract: A wafer defect inspection apparatus including a carrier base, a light source module, a beam splitter, filters and image sensors are provided. The carrier base carries a sample to be tested. The light source module includes an illuminating unit and a pellicle mirror. The illuminating unit emits an inspection light ray. A reflective surface is capable of reflecting the inspection light ray to the sample to be tested, so that a reflective light ray formed by reflecting the inspection light ray reflected by the sample to be tested passes through the pellicle mirror and is then split into splitting light rays by the beam splitter. The filters are configured to be passed through by different bands corresponding to the splitting light rays. The image sensors receive the splitting light rays to generate imaging frames. Two corresponding positions in any two of the imaging frames have two different contrast ratios.

Abstract: Various embodiments of the present application are directed towards a pad with high strength and bondability. In some embodiments, an integrated chip comprises a substrate, an interconnect structure, a pad, and a conductive structure. The interconnect structure adjoins the substrate and comprises wires and vias. The wires and the vias are stacked between the pad and the substrate. The conductive structure (e.g., a wire bond) extends through the substrate to the pad. By arranging the wires and the vias between the pad and the substrate, the pad may be inset into a passivation layer of the interconnect structure and the passivation layer may absorb stress on the pad. Further, the pad may contact the wires and the vias at a top wire level. A thickness of the top wire level may exceed a thickness of other wire levels, whereby the top wire level may be more tolerant to stress.

Abstract: A method of treating fatty liver-related diseases in a patient includes administering to the patient a therapeutically effective amount of medicament manufactured from a FGF21 polypeptide, FGF21 fusion protein, or dual-fusion protein of FGF21 polypeptide and GLP-1 or a functional variant thereof.

Abstract: The present disclosure relates to an integrated channel apparatus for a non-heat pump thermal management integrated module and an electric vehicle. The integrated channel apparatus includes a first component and a second component, the first component is provided with a channel group that runs through the first component along a thickness direction and a groove that does not run through the first component, the channel group and the groove are used to accommodate a connecting tube. The second component is provided with multiple strip grooves, each strip groove is provided corresponding to two channels to connect the two channels. During use, the integrated channel apparatus is installed in the non-heat pump thermal management integrated module, and the connecting tubes that need to be connected are placed in the two channels and the strip groove correspondingly connecting the two channels.

Abstract: A micro light-emitting diode display device and a micro light-emitting diode structure. The micro light-emitting diode display device includes a circuit substrate and a plurality of display pixels, the display pixels are arranged on the circuit substrate and are electrically connected with the circuit substrate individually. Each display pixel includes a plurality of series-connection structures, and the light wavelengths of the series-connection structures are different. Each series-connection structure includes at least two micro light-emitting elements, and the light wavelengths of the at least two micro light-emitting elements are within a wavelength range of one color light. The circuit substrate provides a driving voltage to drive the series-connection structures of each display pixel.

Abstract: A method for forming semiconductor devices includes providing a substrate with a conductive pad formed thereon; forming a transparent structure over the substrate, wherein the transparent structure includes a plurality of collimating pillars adjacent to the conductive pad; forming a light-shielding structure over the plurality of collimating pillars and the conductive pad; performing a cutting process to remove one or more materials directly above the conductive pad, while leaving remaining material to cover the conductive pad, wherein the material includes a portion of the light-shielding structure; and performing an etching process to remove the remaining material to expose the conductive pad.

Abstract: A deflecting plate includes a silicon-on-insulator (SOI) substrate. The SOI substrate includes: an insulator layer having a top surface and a bottom surface; a device layer coupled to the insulator layer at the top surface, wherein multiple deflecting apertures are disposed in the device layer, each of which extending from a top open end to a bottom open end through the device layer, and wherein the bottom open end is coplanar with the top surface of the insulator layer; and a handle substrate coupled to the insulator layer at the bottom surface, wherein a cavity is disposed in the handle substrate and extends from a cavity open end to a cavity bottom wall, and wherein the bottom wall is coplanar with the top surface of the insulator layer, such that the bottom open end of each deflecting aperture is exposed to the cavity.

Abstract: An optical element driving mechanism is provided and includes a fixed assembly, a movable assembly, a driving assembly and a stopping assembly. The fixed assembly has a main axis. The movable assembly is configured to connect an optical element, and the movable assembly is movable relative to the fixed assembly. The driving assembly is configured to drive the movable assembly to move relative to the fixed assembly. The stopping assembly is configured to limit the movement of the movable assembly relative to the fixed assembly within a range of motion.

Abstract: A processing method of a processing apparatus is provided, including step 1, step 2, step 3, and step 4. Step 1 is providing an object having a processed surface, and dividing the processed surface into multiple processed regions, where there is at least one workpiece on each processed region. Step 2 is performing path computation according to the workpiece on each processed region, and generating a processing path in each processed region, where the processing paths in the processed regions are different from each other. Step 3 is performing processing operation by a processing apparatus according to the processing path in one of the processed regions obtained from step 2. Step 4 is moving the processing apparatus to a next processed region after finishing the processing operation on each workpiece in the one of the processed regions. A processing system is also provided.

Abstract: A processor-implemented method for a neural architecture search (NAS) starts by generating an over-parameterized super network having multiple layers. The super network has multiple operator types. Each of the layers includes a largest super kernel corresponding to a search space. The method also includes performing gradient descent to evolve a largest super kernel to a small kernel corresponding to the search space in order to generate a range of kernel encodings. The method further includes identifying a subset of kernel encodings from the range of kernel encodings, for each layer of the super network, based on the gradient descent. The method determines a set of candidate architectures based on the subset of kernel encodings, each of the candidate architectures having a different model size. The method selects a target model, from the set of architectures, based on meeting hardware specifications, and then applies the target model.

Abstract: An electrode controls transmittance of a blocking layer over a photodiode of a pixel sensor (e.g., a photodiode of a small pixel detector) by changing oxidation of a metal material included in the blocking layer. By using the electrode to adjust transmittance of the blocking layer, pixel sensors for different uses and/or products may be produced using a single manufacturing process. As a result, power and processing resources are conserved that otherwise would have been expended in switching manufacturing processes. Additionally, production time is decreased (e.g., by eliminating downtime that would otherwise have been used to reconfigure fabrication machines.

Abstract: A semiconductor may include an active region, an epitaxial source/drain formed in and extending above the active region, and a first dielectric layer formed over a portion of the active region. The semiconductor may include a first metal gate and a second metal gate formed in the first dielectric layer, a second dielectric layer formed over the first dielectric layer and the second metal gate, and a titanium layer, without an intervening fluorine residual layer, formed on the metal gate and the epitaxial source/drain. The semiconductor may include a first metal layer formed on top of the titanium on the first metal gate, a second metal layer formed on top of the titanium layer on the epitaxial source/drain, and a third dielectric layer formed on the second dielectric layer. The semiconductor may include first and second vias formed in the third dielectric layer.

Abstract: A carrier structure is provided, in which at least one positioning area is defined on a chip-placement area of a package substrate, and at least one alignment portion is disposed on the positioning area. Therefore, the precision of manufacturing the alignment portion is improved by disposing the positioning area on the chip-placement area, such that the carrier structure can provide a better alignment mechanism for the chip placement operation.