Abstract: An interface device includes a motherboard, a DVI female interface, a DVI male interface, a display, and an eSATA connector. The motherboard includes a SATA controller having at least one group of differential signal pins. The DVI female interface is electronically coupled to the group of differential signal pins. The DVI male interface is coupled to the DVI female interface. The display is electronically coupled to the DVI male interface. The eSATA connector is positioned on a display and includes at least one group of differential signal pins electrically coupled to the DVI male interface. The differential signal pins of the eSATA connector configured to be in communication with the differential signal pins of the SATA controller via the DVI male interface and the DVI female interface.

Abstract: A delay circuit for power sequencing in a computer includes an oscillator; an input pin; a counter; a register; and a comparing controller. The counter detects a voltage of the input pin when each clock signal arrives, resets a number counted by the counter when the voltage of the input pin is detected at logic-low electrical level, and adds a predetermined number when the voltage of the input pin is detected at logic-high electrical level. The controller compares the total number counted by the counter with a preset number, and outputs a control signal when the numbers match. The control signal controls a connected logic circuit to work according to a power sequence.

Abstract: A test method includes: setting test parameters for a test of a plurality of electronic devices in response to a user input; generating a control signal according to the test parameters and sending the control signal to a baseboard management controller of each electronic device to control the baseboard management controller to test the corresponding electronic devices according to the parameter set by the user, and recording the number of the time that the start and shut down operation have been done and the test values which can reflect the running state of the electronic devices in a test file; analyzing the stability of each electronic device by analyzing the test result record in the test file. A test device and computer-readable medium are also disclosed.