Abstract: The disclosure relates to a reconstruction prosthesis including a main section, at least one serpentine structure, and at least one mount section. The at least one serpentine structure is connected to one end of the main section. The at least one mount section is connected to the main section via the at least one serpentine structure. The at least one mount section is configured to be connected to osseous tissue. When the at least one serpentine structure is deformed by force, the relative position of the main section and the at least one mount section is changed.

Abstract: A method includes disposing a plurality of active solder pads and at least one mechanical support solder pad on the substrate. The plurality of active solder pads provide areas for mechanical bonding of the substrate to at least one device contact pad disposed on a semiconductor die. The at least one mechanical support solder pad provides an area for mechanical bonding of the substrate to at least one dummy device contact pad disposed on the semiconductor die. The method further includes mechanically bonding the substrate to the semiconductor die by forming solder joints between the plurality of active solder pads and the at least one device contact pad, and between the at least one mechanical support pad and the at least one dummy device contact pad.

Abstract: A structure and a formation method of a semiconductor device are provided. The method includes forming a dummy gate stack over a semiconductor substrate and forming a spacer element over a sidewall of the dummy gate stack. The spacer element has an inner spacer and a dummy spacer, and the inner spacer is between the dummy spacer and the dummy gate stack. The method also includes forming a dielectric layer to surround the spacer element and the dummy gate stack and replacing the dummy gate stack with a metal gate stack. The method further includes removing the dummy spacer of the spacer element to form a recess between the inner spacer and the dielectric layer. In addition, the method includes forming a sealing element to seal the recess such that a sealed hole is formed between the metal gate stack and the dielectric layer.

Abstract: An electrochromic mirror module including a cover lens, a connecting layer, and an electrochromic device is provided. The connecting layer includes a first absorbing material. The connecting layer connects between the cover lens and the electrochromic device. The electrochromic mirror module is configured to receive an incident light, and the incident light sequentially transmits through the cover plate and the connection layer to reach the electrochromic device. The first absorbing material is configured to absorb light of the incident light, whose wavelength falls in a first spectrum, and the wavelength of the first spectrum fall within the range of 570 nm to 720 nm.

Abstract: A semiconductor structure having a Si substrate heterointegrated with GaN and a method for fabricating the same is disclosed. The method uses a (100) silicon substrate to fabricate a hundred nanometer scale hole and uses wet etching to etch the silicon substrate, thereby exposing the (111) crystal surface of the silicon substrate. The (111) crystal surface is used as a nucleating crystal surface of an AlN buffer layer and GaN. When GaN is grown, silane is reacted with GaN to adjust the concentration of doping silicon atoms into GaN, thereby forming a semiconductor structure having a Si substrate heterointegrated with GaN.

Abstract: A computer-implemented method, system and computer program product for providing predictions tailored for a specific domain. Each field within a set of datasets is classified with a concept defined in a domain specific ontology. After receiving a target field and identifying a target concept tagged to the target field, concepts that have an influential impact directly to the target concept or indirectly to a concept tagged to a field associated with the target field are identified. Fields are then identified as candidates for predictors from the identified concepts using a semantic relationship and a numeric association combined approach. An influential confidence score and a numeric analytics score are then calculated for each of these candidates upon which a final confidence score is computed. The identified candidates are ranked based on the final confidence scores, and the top ranked candidates for predictors are selected to build a statistical model.

Abstract: A method for fabricating semiconductor device includes the steps of first providing a substrate having a fin-shaped structure thereon, forming a single diffusion break (SDB) structure in the substrate to divide the fin-shaped structure into a first portion and a second portion, and then forming more than one gate structures such as a first gate structure and a second gate structure on the SDB structure. Preferably, each of the first gate structure and the second gate structure overlaps the fin-shaped structure and the SDB structure.

Abstract: A method for fabricating semiconductor device includes the steps of: forming a first magnetic tunneling junction (MTJ) on a substrate; forming a first ultra low-k (ULK) dielectric layer on the first MTJ; performing a first etching process to remove part of the first ULK dielectric layer and forming a damaged layer on the first ULK dielectric layer; and forming a second ULK dielectric layer on the damaged layer.

Abstract: A frame module is provided, which is adapted to connect to an object unit. The frame module includes a module housing, a latch, and a cover. The object unit is connected to the module housing. The latch is connected to the module housing, which is adapted to be moved between the first latch position and the second latch position. When the latch is in the first latch position, the latch is connected to the object unit to restrict the object unit. When the latch is in the second latch position, the latch is separated from the object unit. The cover pivots on the module housing, which is adapted to be rotated between the first cover orientation and the second cover orientation. When the cover is in the first cover orientation, the cover presses the latch and keeps the latch in the first latch position.

Abstract: A memory module includes a first redistribution structure, a second redistribution structure, first semiconductor dies, second semiconductor dies, an encapsulant, through insulator vias and thermally conductive material. Second redistribution structure is stacked over first redistribution structure. First semiconductor dies are sandwiched between first redistribution structure and second redistribution structure and disposed side by side. Second semiconductor dies are disposed on the second redistribution structure. The encapsulant laterally wraps the second semiconductor dies. The through insulator vias are disposed among the first semiconductor dies, extending from the first redistribution structure to the second redistribution structure. The through insulator vias are electrically connected to the first redistribution structure and the second redistribution structure.

Abstract: A battery tray and a vehicle include a frame structure including a plurality of frames sequentially connected end to end arranged to be connected to the vehicle, and a base plate structure including an inner base plate and a reinforcing beam, wherein the inner base plate is located on an inner side of the reinforcing beam and arranged for mounting a battery module. The battery tray further includes a reinforcing block, wherein the reinforcing block is connected to a corresponding frame and the reinforcing beam in a matching mode, so as to fixedly connect the reinforcing beam to the frame structure through the reinforcing block. In the battery tray, the strength of the battery tray can be enhanced and a total weight can be decreased only by using the reinforcing block to fixedly connect the reinforcing beam to the frame structure.

Abstract: A chip package structure includes a substrate, at least two chips, a plurality of first pads, a plurality of first micro bumps, and a bridging element. The substrate has a first surface and a second surface opposite to the first surface. The two chips are disposed on the first surface of the substrate and are horizontally adjacent to each other. Each chip has an active surface. The first pads are disposed on the active surface of each of the chips. The first micro bumps are disposed on the first pads and have the same size. The bridging element is disposed on the first micro bumps such that one of the chips is electrically connected to another of the chips through the first pads, the first micro bumps, and the bridging element.

Abstract: A nickel-iron alloy hydrogenation catalyst and a fabricating method thereof are provided. The nickel-iron alloy hydrogenation catalyst has 65 to 95 atomic percent nickel; and 5 to 35 atomic percent of iron, wherein the nickel-iron alloy hydrogenation catalyst is spherical and has an average particle diameter of 180 to 300 nm. The nickel-iron alloy hydrogenation catalyst is present in a non-carrier form. The nickel-iron alloy hydrogenation catalyst can generate a hydrogenation reaction at a low temperature (about 130˜140° C.) and has a high conversion rate (compared to pure nickel catalyst).

Abstract: The present disclosure describes a semiconductor structure having a power distribution network including first and second conductive lines. A substrate includes a first surface that is in contact with the power distribution network. A plurality of backside vias are in the substrate and electrically coupled to the first conductive line. A via rail is on a second surface of the substrate that opposes the first surface. A first interlayer dielectric is on the via rail and on the substrate. A second interlayer dielectric is on the first interlayer dielectric. A third interlayer dielectric is on the second interlayer dielectric. First and top interconnect layers are in the second and third interlayer dielectrics, respectively. Deep vias are in the third interlayer dielectric and electrically coupled to the via rail. The deep vias are also connected to the first and top interconnect layers. A power supply in/out layer is on the third interlayer dielectric and in contact with the top interconnect layer.

Abstract: Provided is a process for manufacturing a graphene material, the process comprising (a) injecting a rust stock into a first end of a continuous reactor having a toroidal vortex flow, wherein the first stock comprises graphite and a non-oxidizing liquid (or, alternatively, graphite, an acid, and an optional oxidizer) and the continuous flow reactor is configured to produce the toroidal vortex flow, enabling the formation of a reaction product suspension or slurry at the second end, downstream from the first end, of the continuous reactor; and (b) introducing the reaction product suspension/slurry from the second end back to enter the continuous reactor at or near the first end, allowing the reaction product suspension/slurry to form a toroidal vortex flow and move down to or near the second end to produce a graphene suspension or graphene oxide slurry. The process may further comprise repeating step (b) for at least one time.

Abstract: The present invention provides a biological morph-genetic WO3 photocatalyst and a preparation method and application thereof, and belongs to the technical field of photocatalysis The preparation method of the present invention includes the following steps: impregnating a rice husk into a tungsten source solution, and roasting an obtained solid material after solid-liquid separation to obtain the biological morph-genetic WO3 photocatalyst.

Abstract: Disclosed by this application is a method for determining the size of a resource block group. The method includes: according to a Radio Network Temporary Identifier (RNTI) used for scrambling Downlink Control Information (DCI) and a BandWidth Part (BWP) size, determining, by a terminal device, a resource block group size used for the DCI to schedule a resource.

Abstract: An in-situ emulsification and viscosity increase system with controllable viscosity consists of the following components in percentage by weight: 0.3˜1.5% of emulsifier, 0.05˜0.5% of ultrafine colloidal particles, 0.01˜0.1% of suspending agent and the balance of mineralized water. The emulsifier is one of or a combination of petroleum sulfonate, petroleum carboxylate, sodium dodecyl sulfate, sodium dodecyl benzenesulfonate, alkyl glycoside, aliphatic alcohol ether carboxylate, aliphatic alcohol ether sulfonate, hydroxysulfobetaine and alkanolamide. The ultrafine colloidal particles are one of ultrafine silicon dioxide, ultrafine montmorillonoid, ultrafine ferric oxide, ultrafine ferroferric oxide, ultrafine aluminum oxide and ultrafine titanium dioxide. The suspending agent is one of partially hydrolyzed polyacrylamide, amylose, carboxymethyl chitosan, hydroxymethyl cellulose, xanthan gum and sodium alginate.

Abstract: An antifuse element includes a conductive region formed in a semiconductor substrate extending in a first direction, a dielectric layer formed on a portion of the conductive region, a first conductive plug formed on the dielectric layer, a second conductive plug formed on another portion of the conductive region, a first conductive member formed over the first conductive plug, and a second conductive member formed over the second conductive plug. The dielectric layer has a first dielectric portion extending in a second direction, and a second dielectric portion extending in the first direction, in which the dielectric layer implements an electrical isolation between the conductive region and the first conductive plug. The first conductive plug has a first region of a first width and a second region of a second width, and the first width is greater than the second width.

Abstract: An integrated circuit design method includes receiving an integrated circuit design, and determining a floor plan for the integrated circuit design. The floor plan includes an arrangement of a plurality of functional cells and a plurality of tap cells. Potential latchup locations in the floor plan are determined, and the arrangement of at least one of the functional cells or the tap cells is modified based on the determined potential latchup locations.