Patents by Inventor An Lin

An Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10347538
    Abstract: A semiconductor device includes a semiconductor fin protruding from a substrate, a gate electrode over the semiconductor fin, a gate insulating layer between the semiconductor fin and the gate electrode, source and drain regions disposed on opposite sides of the semiconductor fin, a first stressor formed in a region between the source and drain regions. The first stressor is a grading strained stressor including multiple graded portions formed at graded depths. The first stressor is configured to create one of a graded compressive stress or a graded tensile stress.
    Type: Grant
    Filed: October 4, 2017
    Date of Patent: July 9, 2019
    Assignees: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., NATIONAL TAIWAN UNIVERSITY
    Inventors: Che-Wei Yang, Hao-Hsiung Lin, Samuel C. Pan
  • Patent number: 10349558
    Abstract: A method of manufacturing a heat dissipating device includes steps of providing a heat dissipating fin and a heat pipe. The heat dissipating fin includes a fin body, a through hole and a collar portion, with the through hole formed on the fin body, with the collar portion extending from a periphery of the through hole and having a first U-shaped protruding ear, with the first U-shaped protruding ear having a first opening, with the heat pipe having a heat dissipating end and a heat absorbing end, and with the heat dissipating end opposite to the heat absorbing end; inserting the heat dissipating end into the through hole and the collar portion; and punching the collar portion to shrink the first opening of the first U-shaped protruding ear, such that the collar portion fixes the heat dissipating end in a tight-fitting manner.
    Type: Grant
    Filed: May 15, 2017
    Date of Patent: July 9, 2019
    Assignee: Cooler Master (Hui Zhou) Co., Ltd.
    Inventors: Chia-Yu Lin, Qingsong Zhang, Tao Song
  • Patent number: 10347574
    Abstract: Integrated fan-out packages and methods of forming the same are disclosed. An integrated fan-out package includes a first semiconductor chip, a plurality of through integrated fan-out vias, an encapsulation layer and a redistribution layer structure. The first semiconductor chip includes a heat dissipation layer, and the heat dissipation layer covers at least 30 percent of a first surface of the first semiconductor chip. The through integrated fan-out vias are aside the first semiconductor chip. The encapsulation layer encapsulates the through integrated fan-out vias. The redistribution layer structure is at a first side of the first semiconductor chip and thermally connected to the heat dissipation layer of the first semiconductor chip.
    Type: Grant
    Filed: January 22, 2018
    Date of Patent: July 9, 2019
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Shin-Puu Jeng, Dai-Jang Chen, Hsiang-Tai Lu, Hsien-Wen Liu, Chih-Hsien Lin, Shih-Ting Hung, Po-Yao Chuang
  • Patent number: 10345157
    Abstract: An on-chip temperature sensing device is disclosed. The disclosed on-chip temperature sensing device is capable of sensing an environmental temperature of the chip. The device comprises a reference generating circuit, a first oscillator, a second oscillator, and an arithmetic logic unit. The reference generating circuit is configured to generate a first control voltage to control the first oscillator and the second oscillator. The bias current of the first oscillator and the bias current of the second oscillator are both controlled by the first control voltage so that the bias current of the first oscillator is directly proportional the bias current of the second oscillator regardless the environmental temperature. The first oscillator generates a first oscillation signal, while the second oscillator generates a second oscillation signal. The arithmetic logic unit may calculate the environmental temperature according to the first oscillation signal and the second oscillation signal.
    Type: Grant
    Filed: April 16, 2014
    Date of Patent: July 9, 2019
    Assignee: SILICON INTEGRATED SYSTEMS CORP.
    Inventor: Song-Sheng Lin
  • Patent number: 10345617
    Abstract: Apparatuses, systems for electronic wearable devices such as smart glasses are described. The wearable device can comprise a frame, an elongate temple and an articulated joint. The frame can define one or more optical element holders configured to hold respective optical elements for viewing by a user in a viewing direction. The temple can be moveably connected to the frame for holding the frame in position when the device is worn by the user. The articulated joint can connect the temple and the frame to permit movement of the temple relative to the frame between a wearable position in which the temple is generally aligned with the viewing direction, and a collapsed position in which the temple extends generally transversely to the viewing direction. The articulated joint can include a base foot fixed to the frame and oriented transversely to the viewing direction.
    Type: Grant
    Filed: July 19, 2017
    Date of Patent: July 9, 2019
    Assignee: Snap Inc.
    Inventors: Nicholas Streets, Jun Lin, Stephen Steger
  • Patent number: 10346944
    Abstract: An apparatus to facilitate processing of a sparse matrix is disclosed. The apparatus includes a plurality of processing units each comprising one or more processing elements, including logic to read operands, a multiplication unit to multiply two or more operands and a scheduler to identify operands having a zero value and prevent scheduling of the operands having the zero value at the multiplication unit.
    Type: Grant
    Filed: April 9, 2017
    Date of Patent: July 9, 2019
    Assignee: INTEL CORPORATION
    Inventors: Eriko Nurvitadhi, Balaji Vembu, Tsung-Han Lin, Kamal Sinha, Rajkishore Barik, Nicolas C. Galoppo Von Borries
  • Patent number: 10344401
    Abstract: A method for manufacturing a nylon 66 hollow fiber includes steps as follows. A plurality of nylon 66 particles are provided. A melting step is provided, wherein the nylon 66 particles are melted so as to form a spun liquid. A fiber spitting step is provided, wherein the spun liquid goes through a hollow spinneret plate so as to form hollow nascent fibers. An evacuating step is provided, wherein the hollow nascent fibers are preliminarily solidified so as to form hollow half-solidified fibers. A cooling step is provided, wherein the hollow half-solidified fibers are cooled and solidified so as to form solidified fibers. A collecting and oiling step is provided. A drawing step is provided. A winding step is provided so as to obtain the nylon 66 hollow fiber.
    Type: Grant
    Filed: January 10, 2016
    Date of Patent: July 9, 2019
    Assignee: CHAIN YARN CO., LTD.
    Inventors: Yen-Hsiao Chen, Chung-Chen Wu, Chi-Lu Huang, Chuan-Shing Lin
  • Patent number: 10345588
    Abstract: Method and devices for creating a sedentary virtual-reality system are provided. A user interface is provided that allows for the intuitive navigation of the sedentary virtual-reality system based on the position of the users head. The sedentary virtual-reality system can render a desktop computing environment. The user can switch the virtual-reality system into an augmented reality viewing mode or a real-world viewing mode that allow the user to control and manipulate the rendered sedentary environment. The modes can also change to allow the user greater situational awareness and a longer duration of use.
    Type: Grant
    Filed: October 13, 2017
    Date of Patent: July 9, 2019
    Assignee: Connectivity Labs Inc.
    Inventors: Rocky Chau-Hsiung Lin, Koichiro Kanda, Thomas Yamasaki
  • Patent number: 10342878
    Abstract: The present invention is related to a compound conjugating a drug with a glycosaminoglycan, such as hyaluronic acid (HA), where the drug is useful for the treatment of diseases such as inflammation, auto-immune disease, allergy, infection and preferably cancer. The conjugated compound of the present invention can increase the concentration of drug at the specific site of disease by an interaction of the glycosaminoglycan used as target drug delivery carrier and the CD44 cell surface receptor, then enhancing the therapeutic efficacy and reducing the systemic side effect of the site-delivered drug.
    Type: Grant
    Filed: January 20, 2017
    Date of Patent: July 9, 2019
    Assignee: HOLY STONE HEALTHCARE CO., LTD.
    Inventor: Hua-Yang Lin
  • Patent number: 10348402
    Abstract: Embodiments of the present application provide a visible light signal receiving and control method, a control apparatus, and a receiving device. The method comprises: determining a communication performance between a visible light signal receiving device and at least one visible light signal transmit device; and in response to an increase in the communication performance between the visible light signal receiving device and the at least one visible light signal transmit device, combining two first logic pixel units of an image sensor related to the at least one visible light signal transmit device as one second logic pixel unit to be read, when reading an inductive charge of the image sensor of the visible light signal receiving device.
    Type: Grant
    Filed: October 10, 2015
    Date of Patent: July 9, 2019
    Assignee: BEIJING ZHIGU RUI TUO TECH CO., LTD.
    Inventors: Ran Xu, Lin Du
  • Patent number: 10345868
    Abstract: A hinge structure including an axis body, a torque member, and a pressing assembly is provided. The axis body includes a contact surface. The torque member leans against the contact surface of the axis body. The torque member and the axis body are rotatable relatively around a central axis of the axis body. The contact surface pushes the torque member to move around the central axis of the axis body when the torque member and the axis body rotate relatively. The pressing assembly provides a pushing force to the torque member to push the torque member to push towards the contact surface. A plurality of electronic devices having the hinge structure are further provided.
    Type: Grant
    Filed: August 18, 2017
    Date of Patent: July 9, 2019
    Assignee: Acer Incorporated
    Inventors: Yu-Chin Huang, Yu-Nan Lin, Wen-Neng Liao
  • Patent number: 10347710
    Abstract: A method for forming a thin film resistor (TFR) without via penetration and the resulting device are provided. Embodiments include forming a first ILD over a substrate; forming a second ILD over the first ILD; forming a first metal layer in the second ILD; forming a first nitride layer over the second ILD and the first metal layer; forming a third ILD over the first nitride layer; forming vias through the third ILD and the first nitride layer, coupled to the first metal layer; forming a TFR layer over two of the vias and the third ILD between the two vias; forming a second nitride layer over the TFR layer and the third ILD; forming a fourth ILD over the second nitride layer; and forming a second metal layer in the fourth ILD and the second nitride layer.
    Type: Grant
    Filed: March 1, 2017
    Date of Patent: July 9, 2019
    Assignee: GLOBALFOUNDRIES SINGAPORE PTE. LTD.
    Inventors: Purakh Raj Verma, Kemao Lin
  • Patent number: 10348876
    Abstract: A flexible screen mobile terminal includes: a first body, a second body, a flexible screen, and a screen support, where the screen support is configured to fix the flexible screen, and enable the flexible screen to be movably connected to at least one of the first body and the second body. The terminal provided by the present disclosure may realize dual requirements for a large-size screen and a small-volume product.
    Type: Grant
    Filed: July 10, 2017
    Date of Patent: July 9, 2019
    Assignee: GUANGDONG OPPO MOBILE TELECOMMUNICATIONS CORP., LTD.
    Inventor: Yugui Lin
  • Patent number: 10347612
    Abstract: A package includes a first package including a device die, a molding compound molding the device die therein, a through-via penetrating through the molding compound, and a first plurality of Redistribution Lines (RDLs) and a second plurality of RDLs on opposite sides of the molding compound. The through-via electrically couples one of the first plurality of RDLs to one of the second plurality of RDLs. The package further includes a second package bonded to the first package, a spacer disposed in a gap between the first package and the second package, and a first electrical connector and a second electrical connector on opposite sides of the spacer. The first electrical connector and the second electrically couple the first package to the second package. The spacer is spaced apart from the first electrical connector and the second electrical connector.
    Type: Grant
    Filed: November 15, 2017
    Date of Patent: July 9, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Jing-Cheng Lin, Chen-Hua Yu, Szu-Wei Lu, Shih Ting Lin, Shin-Puu Jeng
  • Patent number: 10347678
    Abstract: An image sensor is provided. The image sensor includes a microlens array having a plurality of microlenses; and a sensor array having a plurality of photoelectric elements that are arranged into a plurality of macro pixels. Each macro pixel includes a first photoelectric element, a second photoelectric element, a third photoelectric element, and a fourth photoelectric element that receive incident light via a first microlens, a second microlens, a third microlens, and a fourth lens in the plurality of microlenses. The first microlens, the second microlens, the third microlens, and the fourth microlens in each macro pixel have a first initial offset, a second initial offset, a third initial offset, and a fourth initial offset, respectively. The first microlens and the second microlens in each of the plurality of macro pixels further have a first additional offset and a second additional offset, respectively.
    Type: Grant
    Filed: November 16, 2017
    Date of Patent: July 9, 2019
    Assignee: Visera Technologies Company Limited
    Inventors: Wu-Cheng Kuo, Kuo-Feng Lin, Tsung-Lin Wu, Chin-Chuan Hsieh
  • Patent number: 10346727
    Abstract: The present disclosure includes methods and systems for searching for digital visual media based on semantic and spatial information. In particular, one or more embodiments of the disclosed systems and methods identify digital visual media displaying targeted visual content in a targeted region based on a query term and a query area provide via a digital canvas. Specifically, the disclosed systems and methods can receive user input of a query term and a query area and provide the query term and query area to a query neural network to generate a query feature set. Moreover, the disclosed systems and methods can compare the query feature set to digital visual media feature sets. Further, based on the comparison, the disclosed systems and methods can identify digital visual media portraying targeted visual content corresponding to the query term within a targeted region corresponding to the query area.
    Type: Grant
    Filed: February 10, 2017
    Date of Patent: July 9, 2019
    Assignee: ADOBE INC.
    Inventors: Zhe Lin, Mai Long, Jonathan Brandt, Hailin Jin, Chen Fang
  • Patent number: 10347402
    Abstract: A thermal fuse resistor including a ceramic substrate, a resistor body, a temperature sensing body, a first electrode cap, a second electrode cap, a first lead wire, a second lead wire, and a third lead wire. A first end of the ceramic substrate is provided with a first electrode cap, and a second end of the ceramic substrate is provided with a second electrode cap. The first electrode cap includes a main body, an inner end, and an outer end with an opening. The outer end includes an everted edge closely contacting the first end of the ceramic substrate. The main body and the inner end are arranged inside the ceramic substrate. The first lead wire extends outward from an outer end. One end of the third lead wire is electrically connected to the second electrode cap.
    Type: Grant
    Filed: May 23, 2018
    Date of Patent: July 9, 2019
    Assignee: XIAMEN SET ELECTRONICS CO., LTD.
    Inventors: Shunyuan Du, Lyubo Lin, Yousheng Xu, Changzhou Zhang
  • Patent number: 10347317
    Abstract: An integrated circuit includes an artificial intelligence (AI) logic and an embedded memory coupled to the AI logic and connectable to an external processor. The embedded memory includes multiple storage cells and multiple reference units. One or more reference units in the memory are selected for memory access through configuration at chip packaging level by the external processor. The external processor may execute a self-test process to select or update the one or more reference units for memory access so that the error rate of memory is below a threshold. The self-test process may be performed, via a memory initialization controller in the memory, to test and reuse the reference cells in the memory at chip level. The embedded memory may be a STT-MRAM, SOT, OST MRAM, and/or MeRAM memory.
    Type: Grant
    Filed: October 5, 2017
    Date of Patent: July 9, 2019
    Assignee: Gyrfalcon Technology Inc.
    Inventors: Chyu-Jiuh Torng, Lin Yang, Qi Dong, Daniel H. Liu
  • Patent number: D853661
    Type: Grant
    Filed: February 24, 2017
    Date of Patent: July 9, 2019
    Inventor: Yi-Ju Lin
  • Patent number: RE47503
    Abstract: Photodetectors, methods for use in manufacturing photodetectors, and systems including photodetectors, are described herein. In an embodiment, a photodetector includes a plurality of photodiode regions, at least some of which are covered by an optical filter. A plurality of metal layers are located between the photodiode regions and the optical filter. The metal layers include an uppermost metal layer that is closest to the optical filter and a lowermost metal layer that is closest to the photodiode regions. One or more inter-level dielectric layers separate the metal layers from one another. Each of the metal layers includes one or more metal portions and one or more dielectric portions. The uppermost metal layer is devoid of any metal portions underlying the optical filter.
    Type: Grant
    Filed: March 23, 2016
    Date of Patent: July 9, 2019
    Assignee: INTERSIL AMERICAS LLC
    Inventors: Kenneth Dyer, Eric Lee, Xijian Lin