Patents by Inventor An-Lun LO
An-Lun LO has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240106757Abstract: A method of wireless signal transmission management includes transmitting a plurality of data packets to tethering equipment from user equipment to tethering equipment, determining a size of each of the plurality of data packets by the tethering equipment, designating data packets of the plurality of data packets having a specific range of sizes as control signal packets by the tethering equipment, and prioritizing in transmitting the control signal packets to a cellular network by the tethering equipment.Type: ApplicationFiled: September 21, 2023Publication date: March 28, 2024Applicant: MEDIATEK INC.Inventors: Ching-Hao Lee, Yi-Lun Chen, Ho-Wen Pu, Yu-Yu Hung, Jun-Yi Li, Ting-Sheng Lo
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Publication number: 20240069618Abstract: The disclosure provides a power management method. The power management method is applicable to an electronic device. The electronic device is electrically coupled to an adapter, and includes a system and a battery. The adapter has a feed power. The battery has a discharge power. The power management method of the disclosure includes: reading a power value of the battery; determining a state of the system; and discharging power to the system, when the system is in a power-on state and the power value is greater than a charging stopping value, by using the battery, and controlling, according to the discharge power and the feed power, the adapter to selectively supply power to the system. The disclosure further provides an electronic device using the power management method.Type: ApplicationFiled: April 27, 2023Publication date: February 29, 2024Inventors: Wen Che CHUNG, Hui Chuan LO, Hao-Hsuan LIN, Chun TSAO, Jun-Fu CHEN, Ming-Hung YAO, Jia-Wei ZHANG, Kuan-Lun CHEN, Ting-Chao LIN, Cheng-Yen LIN, Chunyen LAI
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Publication number: 20240056944Abstract: A user equipment (UE) in a mobile network is configured to establish a first packet data network (PDN) connection between the UE and an Internet Protocol Multimedia Service (IMS) network of the mobile network via a wireless local area network (WLAN) access point. The first PDN connection is for implementing a voice call. The UE determines that at least one of the UE or the mobile network fails to support Voice over New Radio (VoNR). Responsive to determining that at least one of the UE or the mobile network fails to support Voice over New Radio (VoNR), the UE prevents itself from establishing a connection with a first radio access network (RAN) of the mobile network.Type: ApplicationFiled: December 10, 2021Publication date: February 15, 2024Inventors: Tai-Lun LO, Ching-Wei CHEN, Po-Ying Chuang
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Publication number: 20230326785Abstract: A height adjustable semiconductor wafer support is provided. The height adjustable semiconductor wafer support includes a chuck for supporting a semiconductor wafer, an adjustment mechanism having a top surface for supporting the chuck, and a stage coupled to the adjustment mechanism such that movement of the top surface of the adjustment mechanism relative to the stage changes a distance between the top surface of the adjustment mechanism and a top surface of the stage.Type: ApplicationFiled: June 15, 2023Publication date: October 12, 2023Inventors: Ming SHING, Yichi YEN, Chun Liang CHEN, Kuo Lun LO
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Patent number: 11715665Abstract: A height adjustable semiconductor wafer support is provided. The height adjustable semiconductor wafer support includes a chuck for supporting a semiconductor wafer, an adjustment mechanism having a top surface for supporting the chuck, and a stage coupled to the adjustment mechanism such that movement of the top surface of the adjustment mechanism relative to the stage changes a distance between the top surface of the adjustment mechanism and a top surface of the stage.Type: GrantFiled: February 11, 2020Date of Patent: August 1, 2023Assignee: Taiwan Semiconductor Manufacturing Company LimitedInventors: Ming Shing, Yichi Yen, Chun Liang Chen, Kuo Lun Lo
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Patent number: 11588021Abstract: A trench MOSFET and a manufacturing method of the same are provided. The trench MOSFET includes a substrate, an epitaxial layer having a first conductive type, a gate in a trench in the epitaxial layer, a gate oxide layer, a source region having the first conductive type, and a body region and an anti-punch through region having a second conductive type. The anti-punch through region is located at an interface between the source region and the body region, and a doping concentration thereof is higher than that of the body region. The epitaxial layer has a first pn junction near the source region and a second pn junction near the substrate. N regions are divided into N equal portions between the two pn junctions, and N is an integer greater than 1. The closer the N regions are to the first pn junction, the greater the doping concentration thereof is.Type: GrantFiled: March 25, 2020Date of Patent: February 21, 2023Assignee: Excelliance MOS CorporationInventors: Chu-Kuang Liu, Yi-Lun Lo
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Publication number: 20220408306Abstract: A user equipment (UE) determines that a protocol data unit (PDU) session comprises an adaptable PDU session. The UE determines whether a current energy mode of the UE comprises an energy-saving mode. In response to determining that the current energy mode of the UE comprises the energy-saving mode, the UE establishes the adaptable PDU session in a non-always-on mode; and in response to determining that the current energy mode of the UE does not comprise the energy-saving mode, the UE establishes the adaptable PDU session in an always-on mode. Further, the UE can initially establish a mode of a plurality of adaptable PDU sessions as the non-always-on mode, when connecting to a certain type of network.Type: ApplicationFiled: July 20, 2022Publication date: December 22, 2022Inventors: Po-Ying Chuang, Tai-Lun Lo
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Publication number: 20210343840Abstract: A manufacturing method of a trench MOSFET includes forming a trench gate in an epitaxial layer having a first conductivity type on a substrate, performing implantations of a dopant having a second conductivity type on the epitaxial layer in which an implantation dose is gradually reduced toward the substrate, performing a first drive-in step to diffuse the dopant having the second conductivity type in an upper half of the epitaxial layer to form a body region, implanting a dopant having the first conductivity type on a surface of the epitaxial layer, performing a second drive-in step to diffuse the dopant having the first conductivity type to form a source region, comprehensively implanting the dopant having the second conductivity type at an interface of the body region and the source region to form an anti-punch through region having a doping concentration higher than that of the body region.Type: ApplicationFiled: July 16, 2021Publication date: November 4, 2021Applicant: Excelliance MOS CorporationInventors: Chu-Kuang Liu, Yi-Lun Lo
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Patent number: 11133207Abstract: A method for forming a film is provided. The method includes sequentially placing a first wafer, a second wafer, and a third wafer in a chamber. The first wafer is separated from the second wafer by a first distance, the second wafer is separated from the third wafer by a second distance, and the first distance is smaller than the second distance. At least one process gas is introduced sequentially passing through the first wafer, the second wafer and the third wafer in the chamber.Type: GrantFiled: May 22, 2019Date of Patent: September 28, 2021Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Wen-Bin Yang, Feng-Yu Chen, Jian-Lun Lo
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Publication number: 20210202701Abstract: A trench MOSFET and a manufacturing method of the same are provided. The trench MOSFET includes a substrate, an epitaxial layer having a first conductive type, a gate in a trench in the epitaxial layer, a gate oxide layer, a source region having the first conductive type, and a body region and an anti-punch through region having a second conductive type. The anti-punch through region is located at an interface between the source region and the body region, and a doping concentration thereof is higher than that of the body region. The epitaxial layer has a first pn junction near the source region and a second pn junction near the substrate. N regions are divided into N equal portions between the two pn junctions, and N is an integer greater than 1. The closer the N regions are to the first pn junction, the greater the doping concentration thereof is.Type: ApplicationFiled: March 25, 2020Publication date: July 1, 2021Applicant: Excelliance MOS CorporationInventors: Chu-Kuang Liu, Yi-Lun Lo
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Patent number: 10930527Abstract: A method for processing semiconductor wafers in a furnace is provided. The method includes forming a thin film on each of the semiconductor wafers in a furnace. The furnace includes a first end thermal zone, a middle thermal zone and a second end thermal zone arranged in sequence. The method further includes controlling the temperature of the furnace in a first thermal mode during the formation of the thin film. The method also includes supplying a purging gas into the furnace after the formation of the thin film. In addition, the method includes controlling the temperature of the furnace in a second thermal mode during the supply of the purging gas. The temperature distributions of the furnace are different in the first and second thermal modes.Type: GrantFiled: June 12, 2020Date of Patent: February 23, 2021Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTDInventors: Jian-Lun Lo, Jih-Churng Twu, Feng-Yu Chen, Yuan-Hsiao Su, Yi-Chi Huang, Yueh-Ting Yang, Shu-Han Chao
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Publication number: 20200312685Abstract: A method for processing semiconductor wafers in a furnace is provided. The method includes forming a thin film on each of the semiconductor wafers in a furnace. The furnace includes a first end thermal zone, a middle thermal zone and a second end thermal zone arranged in sequence. The method further includes controlling the temperature of the furnace in a first thermal mode during the formation of the thin film. The method also includes supplying a purging gas into the furnace after the formation of the thin film. In addition, the method includes controlling the temperature of the furnace in a second thermal mode during the supply of the purging gas. The temperature distributions of the furnace are different in the first and second thermal modes.Type: ApplicationFiled: June 12, 2020Publication date: October 1, 2020Inventors: Jian-Lun LO, Jih-Churng TWU, Feng-Yu CHEN, Yuan-Hsiao SU, Yi-Chi HUANG, Yueh-Ting YANG, Shu-Han CHAO
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Patent number: 10741426Abstract: A method for processing semiconductor wafers in a furnace is provided. The method includes forming a thin film on each of the semiconductor wafers. The method further includes controlling the temperature of the furnace in a first thermal mode during the formation of the thin film. In the first thermal mode, a first end thermal zone, a middle thermal zone and a second end thermal zone of the furnace which are arranged in sequence have a gradually increasing temperature. The method also includes controlling the temperature of the furnace in a second thermal mode after the formation of the thin film. In the second thermal mode, the first end thermal zone, the middle thermal zone and the second end thermal zone of the furnace have a gradually decreasing temperature.Type: GrantFiled: February 27, 2018Date of Patent: August 11, 2020Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Jian-Lun Lo, Jih-Churng Twu, Feng-Yu Chen, Yuan-Hsiao Su, Yi-Chi Huang, Yueh-Ting Yang, Shu-Han Chao
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Publication number: 20200075372Abstract: A wafer boat includes at least one support member, at least one set of at least one first fixture member, at least one set of at least one second fixture member, and at least one set of at least one third fixture member. The support member extends in a direction. The set of the first fixture member, the set of the second fixture member, and the set of the third fixture member are supported by the support member and sequentially arranged in the direction. The set of the first fixture member is separated from the set of the second fixture member by a first pitch, and the set of the second fixture member is separated from the set of the third fixture member by a second pitch, in which the first pitch is smaller than the second pitch.Type: ApplicationFiled: May 22, 2019Publication date: March 5, 2020Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Wen-Bin YANG, Feng-Yu CHEN, Jian-Lun LO
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Publication number: 20190297846Abstract: A pet pacifying environmental device includes a base, a cover mounted on the base, and a low-frequency radio wave generator mounted between the base and the cover.Type: ApplicationFiled: March 30, 2018Publication date: October 3, 2019Inventors: Yung-Teng Lo, Feng-Jung Lo, Feng-Yang Lo, Kuo-Lun Lo
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Publication number: 20190096714Abstract: A method for processing semiconductor wafers in a furnace is provided. The method includes forming a thin film on each of the semiconductor wafers. The method further includes controlling the temperature of the furnace in a first thermal mode during the formation of the thin film. In the first thermal mode, a first end thermal zone, a middle thermal zone and a second end thermal zone of the furnace which are arranged in sequence have a gradually increasing temperature. The method also includes controlling the temperature of the furnace in a second thermal mode after the formation of the thin film. In the second thermal mode, the first end thermal zone, the middle thermal zone and the second end thermal zone of the furnace have a gradually decreasing temperature.Type: ApplicationFiled: February 27, 2018Publication date: March 28, 2019Inventors: Jian-Lun LO, Jih-Churng TWU, Feng-Yu CHEN, Yuan-Hsiao SU, Yi-Chi HUANG, Yueh-Ting YANG, Shu-Han CHAO
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Patent number: 10149647Abstract: A weaning readiness indicator is disclosed. The weaning readiness indicator includes a monitor, a memory, a processor, and a display. The monitor monitors a ventilated patient for a predetermined time length and generates a respiratory signal. The memory stores an algorithm, where the algorithm includes performing a nonlinear time frequency analysis on the respiratory signal to obtain a time frequency representation function, extracting one or more features from the time frequency representation function, and computing a weaning readiness index based on the one or more features. The processor is connected to the monitor and the memory, and executes the algorithm. The display is connected to the processor and provides an indication of the weaning readiness index of the ventilated patient. A sleeping status recording device and an air providing system applying nonlinear time frequency analysis are also disclosed.Type: GrantFiled: October 8, 2015Date of Patent: December 11, 2018Assignee: PHYZQ RESEARCH INC.Inventors: Hau-Tieng Wu, Chun-Hung Chen, Sam Hong-Yi Huang, Yu-Lun Lo
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Patent number: 10113986Abstract: Provided is an electrochemical test strip, including: a sampling end disposed on a wide side of the electrochemical test strip to receive a sample; a connection end disposed on another wide side of the electrochemical test strip to connect with a measuring meter; and at least one protrusion disposed on a long side of the electrochemical test strip. A strip board and method for generating the electrochemical test strip are further provided.Type: GrantFiled: July 20, 2016Date of Patent: October 30, 2018Assignee: APEX BIOTECHNOLOGY CORP.Inventors: Ching Yuan Shih, Meng Lun Lo, Wen Chien Jen, Mon Wen Yang
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Publication number: 20180145869Abstract: A debugging method of switches is applied to a server device comprising the switches, a central processing unit (CPU) and a baseboard management controller (BMC). The CPU generates at least one control signal and transmits it to the switches as executing a mission which relates to transmitting a signal generated by a source device to a sink device. At least part of the switches builds a connection relationship according to the control signal and the switches in the connection relationship are electrically connected to the source device and the sink device. When an error occurs to the CPU or the switches during execution of the mission, the CPU resets the connection relationship. The BMC determines whether the error is removed. When the error is not removed, the BMC records the error, resets the server device, and then selectively sets the switches with a preset connection relationship.Type: ApplicationFiled: March 28, 2017Publication date: May 24, 2018Applicants: INVENTEC (PUDONG) TECHNOLOGY CORPORATION, INVENTEC CORPORATIONInventors: Hsiang-Chun HU, Yi-Lun LO
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Patent number: 9971827Abstract: Technologies are described herein for integrating external data from an external system into a client system. A subscription filed is selected. The subscription filed may include a read method and a query method. The read method may define fields of a client cache operating on the client system. The query method may be executed to retrieve, from the external system, field values corresponding to at least a subset of the fields. Upon executing the query method, the read method may also be executed to retrieve, from the external system, additional field values corresponding to a remaining subset of the fields that were not retrieved by executing the query method. The client cache is populated with the field values and the additional field values according to the fields.Type: GrantFiled: November 21, 2014Date of Patent: May 15, 2018Assignee: Microsoft Technology Licensing, LLCInventors: David Koronthaly, Rolando Jimenez-Salgado, Sundaravadivelan Paranthaman, Arshish Cyrus Kapadia, Wei-Lun Lo