Abstract: A package comprises a substrate including a first surface, and an upper conductive layer arranged on the first surface, a first light-emitting unit arranged on the upper conductive layer, and comprises a first semiconductor layer, a first substrate, a first light-emitting surface and a first side wall, a second light-emitting unit, which is arranged on the upper conductive layer, and comprises a second light-emitting surface and a second side wall, a light-transmitting layer arranged on the first surface and covers the upper conductive layer, the first light-emitting unit, and the second light-emitting unit, a light-absorbing layer, which is arranged between the substrate and the light-transmitting layer in a continuous configuration of separating the first light-emitting unit and the second light-emitting unit from each other, and a reflective wall arranged on the first side wall, wherein a height of the reflective wall is lower than that of the light-absorbing layer.

Abstract: A structure and method for improving manufacturing yield of passive device dies are disclosed. The structure includes first and second groups of capacitors disposed on a substrate, an interconnect structure disposed on the first and second groups of capacitors, first and second bonding structures disposed on the first and second conductive lines, respectively, and first and second measurement structures connected to the first and second conductive lines, respectively, and configured to measure electrical properties of the first and second groups of capacitors, respectively. The interconnect structure includes first and second conductive line connected to the first and second groups of trench capacitors, respectively. The first bonding structure is electrically connected to the first group of capacitors and the second bonding structure is electrically isolated from the first and second groups of capacitors. The first and second measurement structures are electrically isolated from each other.

Abstract: A semiconductor die including mechanical-stress-resistant bump structures is provided. The semiconductor die includes dielectric material layers embedding metal interconnect structures, a connection pad-and-via structure, and a bump structure including a bump via portion and a bonding bump portion. The entirety of a bottom surface of the bump via portion is located within an area of a horizontal top surface of a pad portion of the connection pad-and-via structure.

Abstract: A manufacture method of a deodorization fiber includes: a mixing step including mixing zirconium phosphate and a first dispersant including an amine-group compound in a solvent to form a mixture; a grinding step including grinding the mixture until a D90 particle size of zirconium phosphate is 0.1 ?m to 1.5 ?m to form a grinded mixture; a heating and stirring step including heating and stirring the grinded mixture to uniformly distribute zirconium phosphate and the first dispersant in the solvent to form a deodorant; a blending and pelletizing step including blending and pelletizing the deodorant and polyester to form a fiber masterbatch; and a melt spinning step including melt spinning the fiber masterbatch to form the deodorization fiber. A deodorization fiber is further provided.

Abstract: A high-voltage semiconductor device structure is provided. The high-voltage semiconductor device structure includes a semiconductor substrate, a source ring in the semiconductor substrate, and a drain region in the semiconductor substrate. The high-voltage semiconductor device structure also includes a doped ring surrounding sides and a bottom of the source ring and a well region surrounding sides and bottoms of the drain region and the doped ring. The well region has a conductivity type opposite to that of the doped ring. The high-voltage semiconductor device structure further includes a conductor electrically connected to the drain region and extending over and across a periphery of the well region. In addition, the high-voltage semiconductor device structure includes a shielding element ring between the conductor and the semiconductor substrate. The shielding element ring extends over and across the periphery of the well region.

Abstract: Provided are a package structure and a method of forming the same. The method includes providing a first package having a plurality of first dies and a plurality of second dies therein; performing a first sawing process to cut the first package into a plurality of second packages, wherein one of the plurality of second packages comprises three first dies and one second die; and performing a second sawing process to remove the second die of the one of the plurality of second packages, so that a cut second package is formed into a polygonal structure with the number of nodes greater than or equal to 5.

Abstract: A honeycomb tube with a planar frame defining a fluidic path between a first planar surface and a second planar surface. A fluidic interface is located at one end of the planar frame. The fluidic interface has a fluidic inlet and fluidic outlet. The fluidic path further includes a well chamber having an well-substrate with a plurality of wells. The well chamber is arranged in the planar frame between the first or second surface and the well-substrate.

Abstract: A memory device including a base semiconductor die, conductive terminals, memory dies, an insulating encapsulation and a buffer cap is provided. The conductive terminals are disposed on a first surface of the base semiconductor die. The memory dies are stacked over a second surface of the base semiconductor die, and the second surface of the base semiconductor die is opposite to the first surface of the base semiconductor die. The insulating encapsulation is disposed on the second surface of the base semiconductor die and laterally encapsulates the memory dies. The buffer cap covers the first surface of the base semiconductor die, sidewalls of the base semiconductor die and sidewalls of the insulating encapsulation. A package structure including the above- mentioned memory device is also provided.

Abstract: A memory device including a base semiconductor die, conductive terminals, memory dies, an insulating encapsulation and a buffer cap is provided. The conductive terminals are disposed on a first surface of the base semiconductor die. The memory dies are stacked over a second surface of the base semiconductor die, and the second surface of the base semiconductor die is opposite to the first surface of the base semiconductor die. The insulating encapsulation is disposed on the second surface of the base semiconductor die and laterally encapsulates the memory dies. The buffer cap covers the first surface of the base semiconductor die, sidewalls of the base semiconductor die and sidewalls of the insulating encapsulation. A package structure including the above-mentioned memory device is also provided.

Abstract: A honeycomb tube with a planar frame defining a fluidic path between a first planar surface and a second planar surface. A fluidic interface is located at one end of the planar frame. The fluidic interface has a fluidic inlet and fluidic outlet. The fluidic path further includes a well chamber having a well-substrate with a plurality of wells. The well chamber is arranged in the planar frame between the first or second surface and the well-substrate. The well chamber is in fluidic communication between the pre-amplification chamber and the fluidic outlet.

Abstract: A method for manufacturing a semiconductor device is provided. The method includes forming a first transistor over a substrate, wherein the first transistor comprises a first source/drain feature; depositing an interlayer dielectric layer around the first transistor; etching an opening in the interlayer dielectric layer to expose the first source/drain feature; conformably depositing a semimetal layer over the interlayer dielectric layer, wherein the semimetal layer has a first portion in the opening in the interlayer dielectric layer and a second portion over a top surface of the interlayer dielectric layer; and forming a source/drain contact in the opening in the interlayer dielectric layer.

Abstract: A semiconductor device includes a source/drain portion, a metal silicide layer disposed over the source/drain portion, and a transition layer disposed between the source/drain portion and the metal silicide layer. The transition layer includes implantation elements, and an atomic concentration of the implantation elements in the transition layer is higher than that in each of the source/drain portion and the metal silicide layer so as to reduce a contact resistance between the source/drain portion and the metal silicide layer. Methods for manufacturing the semiconductor device are also disclosed.

Abstract: A honeycomb tube with a planar frame defining a fluidic path between a first planar surface and a second planar surface. A fluidic interface is located at one end of the planar frame. The fluidic interface has a fluidic inlet and fluidic outlet. The fluidic path further includes a well chamber having an well-substrate with a plurality of wells. The well chamber is arranged in the planar frame between the first or second surface and the well-substrate. The well chamber is in fluidic communication between the pre-amplification chamber and the fluidic outlet.

Abstract: A honeycomb tube with a planar frame defining a fluidic path between a first planar surface and a second planar surface. A fluidic interface is located at one end of the planar frame. The fluidic interface has a fluidic inlet and fluidic outlet. The fluidic path further includes a well chamber having an well-substrate with a plurality of wells. The well chamber is arranged in the planar frame between the first or second surface and the well-substrate.

Abstract: The present application is generally directed to systems, methods, and devices for diagnostics for sensing and/or identifying pathogens, genomic materials, proteins, and/or other small molecules or biomarkers. In some implementations, a small footprint low cost device provides rapid and robust sensing and identification. Such a device may utilize microfluidics, biochemistry, and electronics to detect one or more targets at once in the field and closer to or at the point of care. In some implementations, the systems and methods herein implement a reader device, an assay cartridge, and a mobile or external device configured to receive abiological sample, test the biological sample, and provide test results to a patient or user associated with the patient. The test results may be packaged with additional information, including symptoms suffered by the patient, a diagnosis, and follow-up instructions.

Abstract: Some embodiments of the methods provided herein relate to amplifying and detecting a target nucleic acid. Some such embodiments include performing a recombinase polymerase amplification (RPA) and, optionally, a second isothermal amplification reaction. In some embodiments, the second isothermal amplification reaction includes loop-mediated isothermal amplification (LAMP). In some embodiments, the second isothermal amplification reaction is performed in conjunction with the RPA. In some embodiments, the second isothermal amplification reaction is performed on amplification products of the RPA. Some embodiments also include detecting the presence of amplification products by measuring a modulation of an electoral signal such as impedance.

Abstract: Embodiments relate to methods, systems and compositions for reducing nonspecific amplification in isothermal amplification reactions. Some embodiments relate to reducing nonspecific amplification in loop-mediated isothermal amplification (LAMP) reactions with certain oligonucleotides.

Abstract: Some embodiments of the systems, devices, kits and methods provided herein relate to amplifying and detecting a target nucleic acid. Some such embodiments include a droplet comprising an aqueous reaction mixture and an oil, and a detection unit. Some embodiments include a passageway or conduit configured to transport the droplet. In some embodiments, the detection unit includes an electric field-generating unit and an electro-sensing element.

Abstract: A honeycomb tube with a planar frame defining a fluidic path between a first planar surface and a second planar surface. A fluidic interface is located at one end of the planar frame. The fluidic interface has a fluidic inlet and fluidic outlet. The fluidic path further includes a well chamber having an well-substrate with a plurality of wells. The well chamber is arranged in the planar frame between the first or second surface and the well-substrate.