Abstract: A method and apparatus for performing dynamic recovery management regarding a RAID are provided. The method includes: writing a first set of protected data into a first protected access unit of multiple protected access units of the RAID, and recording a first set of management information corresponding to the first set of protected data, for data recovery of the first set of protected data; and when any storage device of multiple storage devices of the RAID malfunctions, writing a second set of protected data into a second protected access unit of the protected access units, and recording a second set of management information corresponding to the second set of protected data, for data recovery of the second set of protected data. Any set of the first set of protected data and the second set of protected data includes data and multiple parity-check codes.

Abstract: A semiconductor device and method of forming the same are provided. The semiconductor device includes a substrate, a growth promoting region, a first gate stack, and a second gate stack. The substrate includes a first region and a second region. The growth promoting region is located in a surface of the substrate in the first region. The growth promoting region includes a first implantation species, and a surface of the substrate in the second region is free of the first implantation species. The first gate stack includes a first gate dielectric layer on the substrate in the first region. The second gate stack includes a second gate dielectric layer on the substrate in the second region.

Abstract: A method and apparatus for performing mapping information management regarding a RAID are provided. The method includes: writing data into a data region of the RAID in a redirect-on-write (ROW) manner, and recording mapping information between logical addresses of the data and protected-access-unit addresses (p-addresses) of protected access units in the data region into a logical-address-to-p-address (L2p) table within a table region of the RAID; when partial data of the data is updated, maintaining an updating list including a set of L2p table entries for the partial data in a RAM, and maintaining a recovery log corresponding to the updating list in a log region of the RAID, for power failure recovery; and according to the updating list, detecting whether a number of same-location L2p table entries in the set of L2p table entries reaches a predetermined threshold, to selectively update the L2p table with the same-location L2p table entries.

Abstract: Provided is a semiconductor device includes a gate stack, a first doped region, a second doped region, a first lightly doped region and a second lightly doped region. The gate stack is disposed on a substrate. The first doped region is located in the substrate at a first side of the gate stack. The second doped region is located in the substrate at a second side of the gate stack. The first lightly doped region is located in the substrate between the gate stack and the first doped region. The second lightly doped region is located in the substrate between the gate stack and the second doped region. A property of the first lightly doped region is different from a property of the second lightly doped region.

Abstract: A multi-axis aircraft with a wind resistant unit includes a fuselage having an upper face and a lower face. The fuselage includes a central axis passing through the upper face and the lower face. A plurality of rotors is mounted to the fuselage. Each rotor includes a rotating axis parallel to the central axis. A wind resistant unit includes a plurality of wind barriers disposed in a radial direction perpendicular to a reference axis. Each wind barrier includes a plurality of rods fixed by at least one fixing member. Two adjacent rods have a passage therebetween. Each rod includes an axis proximal end facing the reference axis and an axis remote end remote to the reference axis. Each wind barrier includes a coupling end and an airflow diversion end. The coupling end is fixed by at least one coupling member to the upper face of the fuselage.

Abstract: A method for forming a semiconductor device structure is provided. The method includes providing a semiconductor substrate. The method includes forming an isolation structure in the semiconductor substrate. The isolation structure surrounds a first active region and a second active region of the semiconductor substrate. The method includes forming a semiconductor strip structure over the semiconductor substrate. The semiconductor strip structure extends across the first active region, the second active region, and the isolation structure between the first active region and the second active region, the semiconductor strip structure has a P-type doped region, an N-type doped region, and a spacing region. The method includes performing an implantation process over the spacing region. The method includes forming a metal silicide layer over the semiconductor strip structure to cover the P-type doped region, the N-type doped region, and the spacing region.

Abstract: A method of forming a protective film on at least one electronic module is provided. The method includes the following steps. A protective material is disposed on at least one electronic module such that the protective material and the electronic modules are in contact with each other. The electronic modules and the protective material disposed on the electronic modules are disposed in a chamber, and a first ambient pressure is provided in the chamber. The protective material in the chamber is heated to a first temperature to soften the protective material disposed on the electronic modules. After the protective material is softened, a second ambient pressure greater than the first ambient pressure is provided in the chamber, wherein a gas in the chamber directly pressurizes the protective material such that the protective material conformally covers a top of the electronic modules.

Abstract: A memory circuit includes a plurality of banks and a controller, each bank of the plurality of banks includes a plurality of segments, and each segment of the plurality of segments includes a plurality of bit lines and a plurality of word lines. A word line switch corresponding to a word line of a segment of the memory circuit is turned on and data are written into memory cells of the segment coupled to a plurality of bit lines of the segment and corresponding to the word line in turn after the controller enables an active command corresponding to the word line. When the controller enables at least one copy row write command, the data are simultaneously written into memory cells sharing a plurality of sense amplifiers with the plurality of bit lines of the segment and corresponding to at least one another word line.

Abstract: A data storage system and a data storage method thereof are provided. The data storage system includes a first server and a second server. The first server is connected to a transmission line, and the first server includes a first data pool and a first controller. The first controller is configured to operate in an active mode. In the active mode, the first controller receives to-be-stored data from a client, stores the to-be-stored data in the first data pool, and sends first storage data through the transmission line. The second server is connected to the first server, and the second server includes a second data pool and a second controller. The second controller is configured to operate in the active mode. In the active mode, the second controller receives the to-be-stored data through the transmission line, and the second controller stores the to-be-stored data in the second data pool.

Abstract: A semiconductor device and a method of manufacturing the same are provided. The semiconductor device includes a gate stack, a first doped region, a second doped region, and a buried doped region. The first doped region has a first conductivity type and is located in the substrate at a first side of the gate stack. The second doped region has the first conductivity type and is located in the substrate at a second side of the gate stack. The buried doped region has the first conductivity type and is buried in the substrate, extended from the first doped region to the second doped region, and separated from the gate stack by a distance.

Abstract: Provided is a semiconductor device includes a gate stack, a first doped region, a second doped region, a first lightly doped region and a second lightly doped region. The gate stack is disposed on a substrate. The first doped region is located in the substrate at a first side of the gate stack. The second doped region is located in the substrate at a second side of the gate stack. The first lightly doped region is located in the substrate between the gate stack and the first doped region. The second lightly doped region is located in the substrate between the gate stack and the second doped region. A property of the first lightly doped region is different from a property of the second lightly doped region.

Abstract: Provided is a semiconductor device includes a gate stack, a first doped region, a second doped region, a first lightly doped region and a second lightly doped region. The gate stack is disposed on a substrate. The first doped region is located in the substrate at a first side of the gate stack. The second doped region is located in the substrate at a second side of the gate stack. The first lightly doped region is located in the substrate between the gate stack and the first doped region. The second lightly doped region is located in the substrate between the gate stack and the second doped region. A property of the first lightly doped region is different from a property of the second lightly doped region.

Abstract: The data storage system includes a memory, a hard disk, and a processing unit. A first logical address and a second logical address in a first logical block of the memory correspond to a piece of duplicated data, and the duplicated data is stored in two physical pages in the hard disk. When executing a de-duplication command, the processing unit transfers the duplicated data to a physical page mapped to a third logical address in a second logical block of the memory; the physical page has a third physical address, and the processing unit updates a first mapping relationship to make it provide a mapping relationship between the first logical address and the third logical address and a mapping relationship between the second logical address and the third logical address, and stores the mapping relationship between the third logical address and the third physical address in the memory.

Abstract: A redundant disk array system and a data storage method thereof are provided. The redundant disk array system includes a plurality of disks, a plurality of data stripes, and a processing unit. The processing unit stores, in a log manner into a write page, first logic page numbers corresponding to the pieces of write data, and records write locations of the first logic page numbers; the processing unit performs garbage collection on invalid page numbers of the first logic page numbers; and after executing garbage collection, the processing unit writes, in a log manner, second logic page numbers corresponding to the pieces of write data into the write pages traversed by a data stripe of the data stripes that has the most invalid page numbers, and records write locations of the second logic page numbers.

Abstract: Provided is a semiconductor device includes a gate stack, a first doped region, a second doped region, a first lightly doped region and a second lightly doped region. The gate stack is disposed on a substrate. The first doped region is located in the substrate at a first side of the gate stack. The second doped region is located in the substrate at a second side of the gate stack. The first lightly doped region is located in the substrate between the gate stack and the first doped region. The second lightly doped region is located in the substrate between the gate stack and the second doped region. A property of the first lightly doped region is different from a property of the second lightly doped region.

Abstract: A data storage method and a system thereof are disclosed. The data storage method includes allocating a first logical block and a second logical block, which are mapped to a physical block; the first logical block includes consecutive first logical pages, used to store logical addresses, and the second logical block includes consecutive second logical pages; on executing garbage collection, sequentially and consecutively storing valid logical addresses in second logical pages in the order of the second logical pages according to valid bits; and establishing a one-to-one second mapping relationship between the second logical pages and valid data pages according to the first mapping relationship.

Abstract: The present invention provides a data storage system and method. A controller is connected to a plurality of disk arrays, and each disk array is provided with a data protection unit for data protection. When one disk drive of one of the disk arrays is damaged, this disk array is defined as a damaged disk array, while other disk arrays without disk drives being damaged are defined as at least one normal disk array. The controller stops to write a new written data into the damaged disk array, while write the new written data into the normal disk arrays. The new written data will be protected by the data protection units of the normal disk arrays. Thereby, continuous data protection for the new written data by the data protection units together with preservation of storage performance of the system, after the disk drive is damaged, may be achieved.

Abstract: A circuit for outputting information of a memory circuit during a self-refresh mode includes a driver. The driver is coupled to a self-refresh control circuit and a self-refresh address counter. The driver is used for driving a plurality of pads of the memory circuit to output information of a plurality of inner signals corresponding to a self-refresh mode signal, and output information of addresses of a plurality of word lines of the memory circuit when the self-refresh mode signal and a test mode signal are enabled and the memory circuit enters the self-refresh mode. Each word line of the plurality of word lines corresponds to an inner signal of the plurality of inner signals.

Abstract: Immunoglobulin chains or antibodies having light or heavy chain complementarity determining regions of antibodies that bind to P-Selectin Glycoprotein Ligand-1. Also disclosed are methods of inducing death of an activated T-cell and of modulating a T cell-mediated immune response in a subject.